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參數(shù)資料
| 型號(hào)： | HTG2190 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit 1024 Pixel LCD Microcontroller |
| 中文描述： | 8位單片機(jī)1024像素LCD |
| 文件頁(yè)數(shù)： | 25/64頁(yè) |
| 文件大小： | 417K |
| 代理商： | HTG2190 |
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HTG2190
Rev. 1.00
25
June 29, 2001
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a warm reset that resets only the PC
and SP, leaving the other circuits in their origi-
nal state. Some registers remain unchanged
during any other reset conditions. Most regis-
ters are reset to their "initial condition" when
the reset conditions are met. By examining the
PD flag and TO flag, the program can distin-
guish between different "chip resets".
TO
PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal
operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal
operation
1
1
WDT wake-up HALT
Note: "u" stands for "unchange"
To guarantee that the system oscillator has
started and stabilized, the SST (System
Start-up Timer) provides an extra-delay of
1024 system clock pulses after a system power
up or when awakening from a HALT state.
When a system power up occurs, the SST delay
is added during the reset period. But when the
reset comes from the RES pin, the SST delay is
disabled. Any wake-up from HALT will enable
the SST delay.
The functional unit chip reset status is shown
in the table.
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master
reset, WDT begins
counting
Timer/event
Counter (0/1/2/3)
Off
LCD Display
Enable
Pull-high of TMR0
/TMR1
With pull-high resis-
tor
Input/output Ports
Input mode
SP
Points to the top of
the stack
&8
# & &
Reset timing chart
Reset circuit
,
: "
,
8
-
,
&
C8&
8
- &
Reset configuration
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