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參數(shù)資料
| 型號： | HTG2190 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit 1024 Pixel LCD Microcontroller |
| 中文描述： | 8位單片機1024像素LCD |
| 文件頁數(shù)： | 37/64頁 |
| 文件大小： | 417K |
| 代理商： | HTG2190 |
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;* use master mode
;* serial clock=F1/2
;*
serial
serc
data
equ 2Ah
equ 29h
equ 51h
org
jmp
;serialdatabuffer
;serial control register
;
004h
serial_op
;serial
;
;
serialap:
;serial function testing (PA=16h)
mov
mov
mov
set
a,55h
data,a
serial,a
pbc
;write data to serial register
;set port B I/P
serail_I:
clr
mov
mov
pbc.5
a,00000111b
serc,a
;serial clock output
;SCLKX=F1/2
;latch data (h->1)
wait:
sz
pb.2
;
HTG2190
Rev. 1.00
37
June 29, 2001
At initial reset, the slave mode (external clock
mode) is selected. Moreover, the synchronous
clock, along with the input/output of the 8 bits
serial data, is controlled as follows:
At master mode, after output of 8 clock from
the SCLK terminal, clock output is automati-
cally suspended and SCLK terminal is fixed
at high level.
At slave mode, after input of 8 clocks to the
terminal, subsequent clock inputs are
masked.
Serial data output
By setting the parallel data to serial data regis-
ters SERDATA individually and writing "0" to
SERC.0, it synchronizes with the synchronous
clock and serial data is output at the SOUT ter-
minal.
When the output of the 8 bits data from D0~D7
is completed, the interrupt factor flag is set to
"1" and interrupt is generated. Moreover, the
interrupt can be masked by the interrupt mask
register INTC.
Note, however, that regardless of the setting of
the interrupt mask register, the interrupt fac-
tor flag is set to "1" after output of the 8 bits
data.
Serial data input
By writing "0" to SERC.0, the serial data is in-
put from the SIN terminal, synchronizes with
the synchronous clock, and is sequentially read
in the 8 bits shift register.
The input data will be fetched at the rising edge
(.1="0") of SCLK. When the input of the 8 bits
data from D0~D7 is completed, the interrupt
factor flag EIF is set to "1" and interrupt is gen-
erated. Moreover, the interrupt can be masked
by the interrupt mask register SERDATA.
Note, however, that regardless of the setting of
the interrupt mask register, the interrupt fac-
torflagissetto"1"afterinputofthe8bitsdata.
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