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參數資料
| 型號： | HTG2190 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit 1024 Pixel LCD Microcontroller |
| 中文描述： | 8位單片機1024像素LCD |
| 文件頁數： | 27/64頁 |
| 文件大小： | 417K |
| 代理商： | HTG2190 |
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HTG2190
Rev. 1.00
27
June 29, 2001
Label
Bits
Function
0~2
Unused bit, read as 0
TE
3
Defines the TMR0/TMR1 active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
Enable/disable timer counting
(0=disabled; 1=enabled)
5
Unused bit, read as 0
TM1, TM0
7, 6
Define the operating mode (TM1, TM0)
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Unused
00=Unused
TMR0C/TMR1C register
Label
Bits
Function
FAST
0
0=speed-up 32K x'tal (default)
1=Non-speed-up 32K x'tal
RTF
1
Select the R-to-F function
0=disable R-to-F (default), 1=enable R-to-F
RTMR0
2
Select the TMR0 pull-high resistor (1=with pull-high; 0=without pull-high)
RTMR1
3
Select the TMR1 pull-high resistor (1=with pull-high; 0=without pull-high)
VDET
4
Supply voltage detection circuit (1=enable VDET, 0=disable VDET)
5~7
Unused bit, read as "0"
X'TALC register
Counter 1 operates in the same manner as
Timer/Event Counter 0.
The TMR0C is the Timer/Event Counter 0 con-
trol register, which defines the Timer/Event
Counter 0 options. The Timer/Event Counter 1
has the same options as the Timer/Event Coun-
ter 0 and is defined by TMR1C.
The timer/event counter control registers de-
fine the operating mode, counting enable or dis-
able and active edge.
The TM0, TM1 bits define the operating mode.
The event count mode is used to count external
events, which implies that the clock source co-
mes from an external (TMR0/TMR1) pin. The
timer mode functions as a normal timer with
the clock source coming from the instruction
clock. The pulse width measurement mode can
be used to count the high or low level duration
of an external signal (TMR0/TMR1). The count-
ing method is based on the instruction clock.
In the event count or timer mode, once the
timer/event counter starts counting, it will
count from the current contents in the
timer/event counter to FFFFH. Once overflow
occurs, the counter is reloaded from the
timer/event counter preload register and gener-
ates a corresponding interrupt request flag
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