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| 型號(hào)： | HY27SS561M |
| 廠(chǎng)商： | Hynix Semiconductor Inc. |
| 英文描述： | 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash |
| 中文描述： | 片256Mbit（32Mx8bit / 16Mx16bit）NAND閃存 |
| 文件頁(yè)數(shù)： | 11/44頁(yè) |
| 文件大小： | 733K |
| 代理商： | HY27SS561M |
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Rev 0.7 / Oct. 2004
11
HY27SS(08/16)561M Series
HY27US(08/16)561M Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Table 2. Bus Operation
Note : (1) Only for x16 devices.
(2) WP must be V
IH
when issing a program or erase command.
Table 3: Address Insertion, x8 Devices
Note: (1). A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.
(2). Any additional input cycles will be ignored with tALS > 0ns.
Table4: Address Insertion, x16 Devices
Note: (1). L must be set ''LOW''.
(2). A8 is Don't Care in x16 devices.
(3). Any additional input cycles will be ignored with tALS > 0ns.
(4). A1 is the Least Significant Address for x16 devices.
(5). The 01h Command is not used in x16 devices.
BUS Operation
CE
ALE
CLE
RE
WE
WP
I/O
0
- I/O
7
I/O
8
- I/O
15(1)
Command Input
V
IL
V
IL
V
IH
V
IH
Rising
X
(2)
Command
X
Address Input
V
IL
V
IH
V
IL
V
IH
Rising
X
Address
X
Data Input
V
IL
V
IL
V
IL
V
IH
Rising
X
Data Input
Data Input
Data Output
V
IL
V
IL
V
IL
Falling
V
IH
X
Data Output
Data Output
Write Protect
X
X
X
X
X
V
IL
X
X
Standby
V
IH
X
X
X
X
X
X
X
Bus Cycle
I/O
7
A7
I/O
6
A6
I/O
5
A5
I/O
4
A4
I/O
3
A3
I/O
2
A2
I/O
1
A1
I/O
0
A0
1st Cycle
2nd Cycle
A16
A15
A14
A13
A12
A11
A10
A9
3rd Cycle
A24
A23
A22
A21
A20
A19
A18
A17
Bus Cycle
I/O
8
-IO
15
L
(1)
L
(1)
L
(1)
I/O
7
A7
I/O
6
A6
I/O
5
A5
I/O
4
A4
I/O
3
A3
I/O
2
A2
I/O
1
A1
I/O
0
A0
1st Cycle
2nd Cycle
A16
A15
A14
A13
A12
A11
A10
A9
3rd Cycle
A24
A23
A22
A21
A20
A19
A18
A17
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