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參數(shù)資料
| 型號(hào)： | ISD-300A1 |
| 英文描述： | Universal Serial Bus |
| 中文描述： | 通用串行總線 |
| 文件頁數(shù)： | 16/67頁 |
| 文件大小： | 580K |
| 代理商： | ISD-300A1 |
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ISD-300A1
11
October 19, 2001
Address
Field Name
Description
On-board
ROM Defaults
0x8
Initialization Status
Force ATA Device
Skip ATA / ATAPI
Device Initialization
Obsolete
Last LUN Identifier
Bit (7) – read only
Drive Initialization Status
If set, indicates the drive initialization sequence state machine is active
Bit (6)
Allows software to manually enable ATA Translation with devices that do
not support ISD-300A1 device initialization algorithms.
Note: Force ATA
Device must be set’1’ in conjunction with Skip ATA/ATAPI Device
Initialization and ATA Translation Enable
. Software must issue an
INQUIRY command followed with a MSC reset to allow the ISD-300A1 to
parse drive information and optimize system performance and operation.
Force ATA Device should be set ‘0’ for devices that support ISD-300A1
device initialization algorithms.
Bit (5)
Skip_Init – This bit should be cleared for I_MODE operation
.
The host
driver must initialize the attached device (if required) when this bit is set.
Note:For ATAPI devices, if Skip_Init is set the host driver must issue an
IDENTIFY command utilizing ATACBs to allow the ISD-300A1 to parse
drive information and optimize system performance and operation. Refer to
bmATACBActionSelect in the
ATA Command Block
-
Field Descriptions
section on page 30 for further information.
0
normal operation
1
only reset the device and write the device control register prior to
processing commands.
Bit (4:3) – Shall be set to ‘0’
Bits (2:0)
Maximum number of LUNs device supports.
Bits (7) – read only.
Current logic state of the ATA_EN pin
Bit (6:1) – Shall be set to 0
Bit (0)
SRST reset during drive initialization. Setting this bit enables the SRST reset
algorithm in the drive initialization state machines.
Bits (7:4)
Standard values for ATA compliant devices and a 30.0 MHz system clock (in
binary).
Note: These values are only valid when the Override PIO Timing
configuration bit is set.
mode 0 0101 (5+1)*33.33 = 200 ns
mode 1 0011 (3+1)*33.33 = 133 ns
mode 2 0011 (3+1)*33.33 = 133 ns
mode 3 0010 (2+1)*33.33 = 100 ns
mode 4 0010 (2+1)*33.33 = 100 ns
Bits (3:0)
ATA cycle times are calculated using Data Assert and Data Recover values.
Standard recover values and cycle times for ATA compliant devices and a
30.0 MHz system clock (in binary).
Note: These values are only valid when
the Override PIO Timing configuration bit is set.
mode 0 1100 (4+1)+(12+1)*33.33 = 600 ns
mode 1 0111 (3+1)+(7+1)*33.33 = 400 ns
mode 2 0011 (2+1)+(3+1)*33.33 = 233 ns
mode 3 0010 (2+1)+(2+1)*33.33 = 200 ns
mode 4 0000 (2+1)+(0+1)*33.33 = 133 ns
0x00
0x9
ATA_EN
Obsolete
SRST Enable
0x01
0xA
ATA Data Assert
ATA Data Recover
0x5C
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