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參數資料
型號： ISD-300A1
英文描述： Universal Serial Bus
中文描述： 通用串行總線
文件頁數： 3/67頁
文件大?。?/td> 580K
代理商： ISD-300A1
ISD-300A1
ii
October 19, 2001
POWER MANAGEMENT........................................................................................................................ 38
C
ONTROL
P
INS
.......................................................................................................................................... 38
VBUS_POWERED Pin........................................................................................................................ 38
DRV_PWR_VALID Pin...................................................................................................................... 39
VBUS_PWR_VALID Pin.................................................................................................................... 39
DISK_READY Pin............................................................................................................................... 39
NLOWPWR Pin................................................................................................................................... 39
NPWR500 Pin...................................................................................................................................... 39
ATA I
NTERFACE
L
INE
S
TATES
.................................................................................................................. 40
OPERATION CONTROL......................................................................................................................... 41
NEJECT, NCART_DET P
INS
– USB R
EMOTE
W
AKEUP AND
E
VENT
N
OTIFICATION
.............................. 41
GPIO P
INS
– G
ENERAL
P
URPOSE
IO......................................................................................................... 41
I_MODE P
IN
– V
ENDOR
S
PECIFIC
I
DENTIFY
(FB
H
) ATA C
OMMAND
(I_MODE).................................... 41
SYS_IRQ P
IN
– USB I
NTERRUPT
............................................................................................................. 41
ATA_EN P
IN
– ATA I
NTERFACE
D
ISABLED
............................................................................................ 42
ATA_PU_EN P
IN
– ATA I
NTERFACE
P
ULL
-
UP
R
ESISTOR
S
OURCE
.......................................................... 42
ATA_PD_EN P
IN
– ATA I
NTERFACE
P
ULL
-
DOWN
R
ESISTOR
S
INK
......................................................... 42
TEST<3:0> P
INS
- T
EST
M
ODES
............................................................................................................... 43
XCVR Mux-out Mode.......................................................................................................................... 43
Limbo Mode......................................................................................................................................... 44
Input NandTree Mode .......................................................................................................................... 44
Bi-di NandTree Mode........................................................................................................................... 44
M
ANUFACTURING
T
EST
M
ODE
.................................................................................................................. 45
EXTERNAL CIRCUITRY........................................................................................................................ 45
ATA I
NTERFACE
C
ONSIDERATIONS
.......................................................................................................... 45
1K Ohm Pull-down Resistor On DD<7>.............................................................................................. 45
ATA_PD_EN and ATA_PU_EN Usage In Self Powered Systems ..................................................... 45
ATA Interface Termination.................................................................................................................. 46
3.3V Power Regulation ........................................................................................................................ 46
VBUS P
OWERED
S
YSTEM
C
ONSIDERATIONS
............................................................................................ 46
GPIO Internal Pull Down Resistors...................................................................................................... 46
ABSOLUTE MAXIMUM RATINGS....................................................................................................... 46
ELECTRICAL CHARACTERISTICS.................................................................................................... 47
V
OLTAGE
P
ARAMETER
.............................................................................................................................. 47
O
PERATION
C
URRENT
P
ARAMETERS
- T
YPICAL
........................................................................................ 47
TIMING CHARACTERISTICS............................................................................................................... 48
I
2
C M
EMORY
D
EVICE
I
NTERFACE
T
IMING
................................................................................................ 48
SYS_IRQ I
NTERFACE
T
IMING
.................................................................................................................. 49
ATA/ATAPI P
ORT
T
IMING
C
HARACTERISTICS
........................................................................................ 49
C
LOCK
....................................................................................................................................................... 49
R
ESET
........................................................................................................................................................ 49
PHYSICAL DIAGRAMS.......................................................................................................................... 50
APPENDIX A – EXAMPLE EEPROM OR FBH IDENTIFY DATA CONTENTS............................ 51
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