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參數資料
| 型號： | ISD-300A1 |
| 英文描述： | Universal Serial Bus |
| 中文描述： | 通用串行總線 |
| 文件頁數： | 32/67頁 |
| 文件大小： | 580K |
| 代理商： | ISD-300A1 |
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ISD-300A1
27
October 19, 2001
READ_MFG_DATA
This USB request returns a “snapshot in time” of select ISD-300A1 input pins. The input pin states are bit-
wise mapped to the USB data packed associated with this request. ISD-300A1 input pins not associated
directly with USB operation can be sampled at any time during normal or Manufacturing Test Mode
operation. This request is independent of normal ISD-300A1 state machine control or Manufacturing Test
Mode write operations. See
Table 14 – READ_MFG_DATA Data Block Bit Map
for an explanation of
the READ_MFG_DATA data packet format.
Legal values for wValue are as follows:
0x0000
wValue must be set to 0x0000.
Legal values for wLength are as follows:
0x0001 –
0x0008
Any data packet lengths greater than 0x0008 will result in a STALL condition.
Table 14
shows the bit-wise input pin mapping of the data packet associated with the READ_MFG_DATA
vendor specific USB command. All input and bi-directional pin values are taken from the pin.
Byte
Bit(s)
0
0
DRV_PWR_VALID
0
1
VBUS_PWR_VALID
0
2
VBUS_POWERED
0
3
DISK_READY
0
3
SYS_IRQ
0
5
IORDY
0
6
DMARQ
0
7
I_MODE
1
0
NCART_DET
1
1
N_EJECT
1
3:2
NLED[1:0]
1
4
NPRW500
(output register value only)
1
5
NATA_RESET
(output register value only)
1
6
NDIOW
(output register value only)
1
7
NDIOR
(output register value only)
2
0
NDMACK
(output register value only)
2
1
ATA_PU_EN
(output register value only)
2
2
ATA_PD_EN
(output register value only)
2
4:3
NCS[1:0]
(output register value only)
2
7:5
DA[2:0]
(output register value only)
3
7:0
DD[7:0]
4
7:0
DD[15:8]
5
7:0
GPIO[7:0]
6
1:0
GPIO[9:8]
6
2
DD[15:0] 3-State Control
(internal register)
6
7:3
GPIO[4:0] 3-State Control
(internal register)
7
4:0
GPIO[9:5] 3-State Control
(internal register)
7
5
MFG_SEL
(manufacturing test mode enable)
7
6
NLOWPWR
(output register value only)
7
7
ATA_EN
Pin Name
Table 14 – READ_MFG_DATA Data Block Bit Map
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