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參數資料
| 型號： | ISP1161 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | 全速通用串行總線的單芯片主機和設備控制器 |
| 文件頁數： | 28/127頁 |
| 文件大小： | 2762K |
| 代理商： | ISP1161 |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
28 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
ATL buffer length = 400H, ITL buffer length = 200H.
This is insufficient use of the internal FIFO buffer RAM.
ATL buffer length = 1000H, ITL buffer length = 0H.
This will use the internal FIFO buffer RAM for only ATL transfers.
ATL buffer length = 0H, ITL buffer length = 800H.
This will use the internal FIFO buffer RAM for only ISO transfers.
The actual requirement for the buffer RAM may not reach the maximum size. You can
make your selection based on your application.
The following are some calculations of the ISO_A or ISO_B space for a frame of data:
Maximum number of useful data sent during one USB frame is 1280 bytes (20 ISO
packets of 64 bytes). Total RAM size needed for this is 20
×
8 + 1280 = 1440 bytes.
Maximum number of packets for different endpoints sent during one USB frame is
150 (150 ISO packets of 1 byte). Total RAM size needed is
150
×
8 + 150
×
1 = 1350 bytes.
The Ping buffer RAM (ITL0) and the Pong buffer RAM (ITL1) have a maximum size
of 2 kbytes each. All data needed for one frame can be stored in the Ping or the
Pong buffer RAM.
When the embedded system wants to initiate a transfer to the USB bus, the data
needed for one frame is transferred to the ATL buffer or ITL buffer. The
microprocessor detects the buffer status through the interrupt routines. When the
HcBufferStatus register (2CH - Read only) indicates that buffer is empty, then the
microprocessor can write data into the buffer. When the HcBufferStatus register
indicates that buffer is full, that is data is ready on the buffer, the microprocessor
needs to read data from the buffer.
During every 1 ms, there might be many events to generate interrupt requests to the
microprocessor for data transfer or status retrieval. However, each of the interrupt
types defined in this specification can be enabled or disabled by setting the
Hc
μ
PInterruptEnable register bits accordingly.
Fig 26. HC Internal FIFO buffer RAM partitions.
MGT950
not used
ATL buffer
ITL0
top
bottom
ITL1
ISO data A
FIFO buffer RAM
ISO data B
control/bulk/interrupt
data
programmable
sizes
4 kbytes
ITL buffer
ATL
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1161A1 | Universal Serial Bus single-chip host and device controller |
| ISP1161A1BD | Universal Serial Bus single-chip host and device controller |
| ISP1161A1BM | Universal Serial Bus single-chip host and device controller |
| ISP1161BD | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1161A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1161A1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus single-chip host and device controller |
| ISP1161A1BD | 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1161A1BD,118 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1161A1BD,151 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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