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參數資料
| 型號： | ISP1161 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | 全速通用串行總線的單芯片主機和設備控制器 |
| 文件頁數： | 52/127頁 |
| 文件大小： | 2762K |
| 代理商： | ISP1161 |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
52 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from
the DMA Counter Register. When the internal counter reaches zero an EOT condition
is generated and the DMA operation stops.
Short/empty packet:
Normally, the transfer byte count must be set via a control
endpoint before any DMA transfer takes place. When a short/empty packet has been
enabled as EOT indicator (SHORTP = 1), the transfer size is determined by the
presence of a short/empty packet in the data. This mechanism permits the use of a
fully autonomous data transfer protocol.
When reading from an OUT endpoint, reception of a short/empty packet at an OUT
token will stop the DMA operation after transferring the data bytes of this packet.
When writing to an IN endpoint, a short packet transferred at an IN token will stop the
DMA operation after all bytes have been transferred. If the number of bytes in the
buffer is zero, ISP1161 DC will automatically send an empty packet.
[1]
If short/empty packet EOT is enabled (SHORTP = 1 in DMA Configuration Register) and DMA
Counter Register is zero.
12.4.2
Isochronous endpoints
A DMA transfer to/from an isochronous endpoint can be terminated by any of the
following conditions (bit names refer to the DMA Configuration Register, see
Table 85
):
An external End-Of-Transfer signal occurs on input EOT
The internal DMA Counter Register reaches zero (CNTREN = 1)
An End-Of-Packet (EOP) signal is detected
DMA operation is disabled by clearing bit DMAEN.
Table 13: Summary of EOT conditions for a bulk endpoint
EOT condition
EOT input
DMA Counter Register
Short packet
OUT endpoint
EOT is active
counter reaches zero
short packet is received and
transferred
empty packet is received and
transferred
DMAEN = 0
IN endpoint
EOT is active
counter reaches zero
counter reaches zero in the
middle of the buffer
empty packet is automatically
appended when needed
[1]
DMAEN = 0
Empty packet
DMAEN bit in DMA
Configuration Register
Table 14: Recommended EOT usage for isochronous endpoints
EOT condition
OUT endpoint
EOT input active
do not use
DMA Counter Register zero
do not use
End-Of-Packet
preferred
IN endpoint
preferred
preferred
do not use
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1161A1 | Universal Serial Bus single-chip host and device controller |
| ISP1161A1BD | Universal Serial Bus single-chip host and device controller |
| ISP1161A1BM | Universal Serial Bus single-chip host and device controller |
| ISP1161BD | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1161A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1161A1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus single-chip host and device controller |
| ISP1161A1BD | 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1161A1BD,118 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1161A1BD,151 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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