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參數資料
| 型號： | ISP1161 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | 全速通用串行總線的單芯片主機和設備控制器 |
| 文件頁數： | 97/127頁 |
| 文件大?。?/td> | 2762K |
| 代理商： | ISP1161 |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
97 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
meaningful after a successful transaction. Exception: during DMA access of a
double-buffered endpoint, the buffer pointer automatically points to the secondary
buffer after reaching the end of the primary buffer.
14.2.2
Read Endpoint Status
This command is used to read the status of an endpoint FIFO. The command
accesses the Endpoint Status Register, the bit allocation of which is shown in
Table 91
. Reading the Endpoint Status Register will clear the interrupt bit set for the
corresponding endpoint in the Interrupt Register (see
Table 106
).
All bits of the Endpoint Status Register are read-only. Bit EPSTAL is controlled by the
Stall/Unstall commands and by the reception of a SETUP token (see
Section 14.2.3
).
Code (Hex): 50 to 5F —
read (control OUT, control IN, endpoint 1 to 14)
Transaction —
read 1 word
Table 91: Endpoint Status Register: bit allocation
Bit
7
Symbol
EPSTAL
6
5
4
3
2
1
0
EPFULL1
EPFULL0
DATA_PID
OVER
WRITE
0
R
SETUPT
CPUBUF
reserved
Reset
Access
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Table 92: Endpoint Status Register: bit description
Bit
Symbol
7
EPSTAL
Description
This bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by
an Unstall Endpoint command. The endpoint is automatically
unstalled upon reception of a SETUP token.
A logic 1 indicates that the secondary endpoint buffer is full.
A logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the present packet (0 = DATA
PID, 1 = DATA1 PID).
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous setup information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the setup data has finished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1
the firmware must stop ongoing setup actions and wait for a new
Setup packet.
A logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
reserved
6
5
4
EPFULL1
EPFULL0
DATA_PID
3
OVERWRITE
2
1
SETUPT
CPUBUF
0
-
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1161A1 | Universal Serial Bus single-chip host and device controller |
| ISP1161A1BD | Universal Serial Bus single-chip host and device controller |
| ISP1161A1BM | Universal Serial Bus single-chip host and device controller |
| ISP1161BD | Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1161BM | Full-speed Universal Serial Bus single-chip host and device controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1161A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1161A1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus single-chip host and device controller |
| ISP1161A1BD | 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1161A1BD,118 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1161A1BD,151 | 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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