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參數資料
| 型號： | ISP1181 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件) |
| 中文描述： | 全速通用串行總線接口設備（全速通用串行總線接口器件） |
| 文件頁數： | 30/69頁 |
| 文件大小： | 1655K |
| 代理商： | ISP1181 |
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Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
30 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
12.1.6
Write/Read DMA Configuration
This command defines the DMA configuration of ISP1181 and enables/disables DMA
transfers. The command accesses the DMA Configuration Register, which consists of
2 bytes. The bit allocation is given in
Table 26
. A bus reset will clear bits DMAEN and
AUTOLD (DMA and auto-restart disabled), all other bits remain unchanged.
Code (Hex): F0/F1 —
write/read DMA Configuration
Transaction —
write/read 2 bytes
[1]
Unchanged by a bus reset.
Table 25: Interrupt Enable Register: bit description
Bit
Symbol
31 to 24
-
23 to 10
IEP14 to IEP1
9
IEP0IN
8
IEP0OUT
7, 6
-
5
IENOSOF
4
IESOF
3
IEEOT
2
IESUSP
1
IERESM
0
IERST
Description
reserved; must write logic 0
A logic 1 enables interrupts from the indicated endpoint.
A logic 1 enables interrupts from the control IN endpoint.
A logic 1 enables interrupts from the control OUT endpoint.
reserved
A logic 1 enables 1 ms interrupts upon loss of SOF.
A logic 1 enables interrupt upon SOF detection.
A logic 1 enables interrupt upon EOT detection.
A logic 1 enables interrupt upon detection of ‘suspend’ state.
A logic 1 enables interrupt upon detection of a ‘resume’ state.
A logic 1 enables interrupt upon detection of a bus reset.
Table 26: DMA Configuration Register: bit allocation
Bit
15
Symbol
CNTREN
Reset
0
[1]
Access
R/W
Bit
7
Symbol
Reset
0
[1]
Access
R/W
14
13
12
11
10
9
8
SHORTP
0
[1]
R/W
6
reserved
0
[1]
R/W
5
reserved
0
[1]
R/W
4
reserved
0
[1]
R/W
3
DMAEN
0
R/W
reserved
0
[1]
R/W
2
AUTOLD
0
R/W
reserved
0
[1]
R/W
1
reserved
0
[1]
R/W
0
EPDIX[3:0]
0
[1]
R/W
BURSTL[1:0]
0
[1]
R/W
0
[1]
R/W
0
[1]
R/W
0
[1]
R/W
Table 27: DMA Configuration Register: bit description
Bit
Symbol
15
CNTREN
Description
A logic 1 enables the generation of an EOT condition, when the
DMA Counter Register reaches zero. Bus reset value:
unchanged.
A logic 1 enables short/empty packet mode. When receiving
(OUT endpoint) a short/empty packet an EOT condition is
generated. When transmitting (IN endpoint) an empty packet is
appended when needed. Bus reset value: unchanged.
reserved
Indicates the destination endpoint for DMA, see
Table 7
.
14
SHORTP
13 to 8
7 to 4
-
EPDIX[3:0]
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1181DGG | INDUCTOR 4.7NH +-.3NH 0402 SMD |
| ISP1183 | Low-power Universal Serial Bus interface device with DMA |
| ISP1183BS | Low-power Universal Serial Bus interface device with DMA |
| ISP1301 | Universal Serial Bus On-The-Go transceiver |
| ISP1301BS | Universal Serial Bus On-The-Go transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1181A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ABS,551 | 功能描述:USB 接口集成電路 USB 1.1 ADVANCED DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ABS,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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