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參數資料
| 型號： | ISP1181 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件) |
| 中文描述： | 全速通用串行總線接口設備（全速通用串行總線接口器件） |
| 文件頁數： | 34/69頁 |
| 文件大?。?/td> | 1655K |
| 代理商： | ISP1181 |
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Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
34 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
When a stalled endpoint is unstalled (either by the Set Endpoint Status command or
by receiving a SETUP token), it is also re-initialized. This flushes the buffer: in and if it
is an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.
Code (Hex): 40 to 4F —
write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 50 to 5F —
read (control OUT, control IN, endpoint 1 to 14)
Transaction —
write/read 1 byte
12.2.3
Validate Endpoint Buffer
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in
the buffer is valid and can be sent to the host, when the next IN token is received. For
a double-buffered endpoint this command switches the current FIFO for CPU access.
Remark:
For special aspects of the control IN endpoint see
Section 9.5
.
Code (Hex): 61 to 6F —
validate endpoint buffer (control IN, endpoint 1 to 14)
Transaction —
none
Table 33: Endpoint Status Register: bit allocation
Bit
7
Symbol
EPSTAL
6
5
4
3
2
1
0
EPFULL1
EPFULL0
reserved
OVER
WRITE
0
R
SETUPT
CPUBUF
reserved
Reset
Access
0
0
R
0
R
0
0
R
0
R
0
R/W
R/W
R/W
Table 34: Endpoint Status Register: bit description
Bit
Symbol
7
EPSTAL
Description
Writing a logic 1 will stall the endpoint. The endpoint is
automatically unstalled upon reception of a SETUP token.
Reading this bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
A logic 1 indicates that the secondary endpoint buffer is full.
A logic 1 indicates that the primary endpoint buffer is full.
reserved
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous setup information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the setup data has finished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1
the firmware must stop ongoing setup actions and wait for a new
Setup packet.
A logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
reserved
6
5
4
3
EPFULL1
EPFULL0
-
OVERWRITE
2
1
SETUPT
CPUBUF
0
-
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1181DGG | INDUCTOR 4.7NH +-.3NH 0402 SMD |
| ISP1183 | Low-power Universal Serial Bus interface device with DMA |
| ISP1183BS | Low-power Universal Serial Bus interface device with DMA |
| ISP1301 | Universal Serial Bus On-The-Go transceiver |
| ISP1301BS | Universal Serial Bus On-The-Go transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1181A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ABS,551 | 功能描述:USB 接口集成電路 USB 1.1 ADVANCED DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ABS,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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