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參數資料
| 型號： | ISP1181BDGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus peripheral controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數： | 14/70頁 |
| 文件大小： | 341K |
| 代理商： | ISP1181BDGG |
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Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
14 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.3 Endpoint initialization
In response to the standard USB request, Set Interface, the firmware must program
all 16 ECRs of the ISP1181B in sequence (see
Table 4
), whether the endpoints are
enabled or not. The hardware will then automatically allocate FIFO storage space.
If all endpoints have been configured successfully, the firmware must return an empty
packet to the control IN endpoint to acknowledge success to the host. If there are
errors in the endpoint configuration, the firmware must stall the control IN endpoint.
When reset by hardware or via the USB bus, the ISP1181B disables all endpoints
and clears all ECRs, except for the control endpoint which is fixed and always
enabled.
Endpoint initialization can be done at any time; however, it is valid only after
enumeration.
9.4 Endpoint I/O mode access
When an endpoint event occurs (a packet is transmitted or received), the associated
endpoint interrupt bits (EPn) of the Interrupt Register (IR) will be set by the SIE. The
firmware then responds to the interrupt and selects the endpoint for processing.
The endpoint interrupt bit will be cleared by reading the Endpoint Status Register
(ESR). The ESR also contains information on the status of the endpoint buffer.
For an OUT (= receive) endpoint, the packet length and packet data can be read from
ISP1181B using the Read Buffer command. When the whole packet has been read,
the firmware sends a Clear Buffer command to enable the reception of new packets.
For an IN (= transmit) endpoint, the packet length and data to be sent can be written
to ISP1181B using the Write Buffer command. When the whole packet has been
written to the buffer, the firmware sends a Validate Buffer command to enable data
transmission to the host.
9.5 Special actions on control endpoints
Control endpoints require special firmware actions. The arrival of a SETUP packet
flushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for
the control IN and OUT endpoints. The microcontroller needs to re-enable these
commands by sending an Acknowledge Setup command to
both
control endpoints.
This ensures that the last SETUP packet stays in the buffer and that no packets can
be sent back to the host until the microcontroller has explicitly acknowledged that it
has seen the SETUP packet.
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1181 | Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件) |
| ISP1181DGG | INDUCTOR 4.7NH +-.3NH 0402 SMD |
| ISP1183 | Low-power Universal Serial Bus interface device with DMA |
| ISP1183BS | Low-power Universal Serial Bus interface device with DMA |
| ISP1301 | Universal Serial Bus On-The-Go transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1181BDGG,112 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181BDGG,118 | 功能描述:USB 接口集成電路 USB 1.1 DEVICE CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181BDGG-T | 制造商:ST-Ericsson 功能描述:USB Peripheral Controller 48-Pin TSSOP T/R |
| ISP1181BDGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181BPC | 制造商:ST-Ericsson 功能描述:Full-Speed Universal Serial Bus Peripheral Controller |
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