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參數資料
| 型號： | ISP1181BDGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus peripheral controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數： | 22/70頁 |
| 文件大小： | 341K |
| 代理商： | ISP1181BDGG |
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Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
22 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11.2 Resume conditions
A wake-up from the suspend state is initiated either by the USB host or by the
application:
USB host
: drives a K-state on the USB bus (global resume)
Application
: remote wake-up through a HIGH level on input WAKEUP or a LOW
level on input CS (if enabled using bit WKUPCS in the Hardware Configuration
register). Wake-up on CS will work only if V
BUS
is present.
The steps of a wake-up sequence are as follows:
1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, the
clock signals are routed to all internal circuits of the ISP1181B.
2. The SUSPEND output is deasserted, and bit RESUME in the Interrupt register is
set. This will generate an interrupt if bit IERESM in the Interrupt Enable register is
set.
3. Maximum 15 ms after starting the wake-up sequence, the ISP1181B resumes its
normal functionality.
4. In case of a remote wake-up, the ISP1181B drives a K-state on the USB bus for
10 ms.
5. Following the deassertion of output SUSPEND, the application restores itself and
other system components to the normal operating mode.
6. After wake-up, the internal registers of the ISP1181B are write-protected to
prevent corruption by inadvertent writing during power-up of external
components. The firmware must send an Unlock Device command to the
ISP1181B to restore its full functionality.
11.3 Control bits in suspend and resume
Fig 7.
SUSPEND and WAKEUP signals in a powered-off modem application.
WAKEUP
8031
RST
RING DETECTION
ISP1181B
DP
DM
USB
VBUS
VBUS
VCC
LINE
004aaa672
SUSPEND
Table 12:
Register
Interrupt
Summary of control bits
Bit
SUSPND
BUSTATUS
Function
a transition from awake to the suspend state was detected
monitors USB bus status (logic 1 = suspend); used when
interrupt is serviced
a transition from suspend to the resume state was detected
RESUME
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1181 | Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件) |
| ISP1181DGG | INDUCTOR 4.7NH +-.3NH 0402 SMD |
| ISP1183 | Low-power Universal Serial Bus interface device with DMA |
| ISP1183BS | Low-power Universal Serial Bus interface device with DMA |
| ISP1301 | Universal Serial Bus On-The-Go transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1181BDGG,112 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181BDGG,118 | 功能描述:USB 接口集成電路 USB 1.1 DEVICE CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181BDGG-T | 制造商:ST-Ericsson 功能描述:USB Peripheral Controller 48-Pin TSSOP T/R |
| ISP1181BDGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181BPC | 制造商:ST-Ericsson 功能描述:Full-Speed Universal Serial Bus Peripheral Controller |
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