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參數資料
型號: ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數: 73/150頁
文件大小: 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
73 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.1.3
HcCommandStatus register (R/W: 02H/82H)
The HcCommandStatus register is a 4-byte register, and the bit allocation is given in
Table 39
. This register is used by the HC to receive commands issued by the HCD,
and it also re
fl
ects the current status of the HC. To the HCD, it appears to be a
write
to set
register. The HC must ensure that bits written as logic 1 become set in the
register while bits written as logic 0 remain unchanged in the register. The HCD may
issue multiple distinct commands to the HC without concern for corrupting previously
issued commands. The HCD has normal read access to all bits.
The SchedulingOverrunCount (SOC)
fi
eld indicates the number of frames with which
the HC has detected the scheduling overrun error. This occurs when the Periodic list
does not complete before the End-of-Frame (EOF). When a scheduling overrun error
is detected, the HC increments the counter and sets the SchedulingOverrun (SO)
fi
eld of the HcInterruptStatus register.
Code (Hex): 02
read
Code (Hex): 82
write
Table 39:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcCommandStatus register: bit allocation
31
30
29
28
27
26
25
24
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
reserved
SOC[1:0]
-
-
-
-
-
-
-
-
-
-
-
-
0
R
9
0
R
8
15
14
13
12
11
10
reserved
-
-
7
-
-
6
-
-
5
-
-
4
-
-
3
-
-
2
-
-
1
-
-
0
reserved
-
-
HCR
0
R/W
-
-
-
-
-
-
-
-
-
-
-
-
相關PDF資料
PDF描述
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