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參數(shù)資料
型號: ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 87/150頁
文件大小: 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
87 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.3.4
HcRhPortStatus[1:2] register (R/W [1]: 15H/95H; [2]: 16H/96H)
The HcRhPortStatus[1:2] register is used to control and report port events on a
per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus
registers that are implemented in hardware. The lower word is used to re
fl
ect the port
status, whereas the upper word re
fl
ects the status change bits. Some status bits are
implemented with special write behavior. If a transaction (token through handshake)
is in progress when a write to change port status occurs, the resulting port status
change must be postponed until the transaction completes. Reserved bits should
always be written logic 0. The bit allocation of the HcRhPortStatus[1:2] register is
given in
Table 61
.
Code (Hex): [1] = 15, [2] = 16
read
Code (Hex): [1] = 95, [2] = 96
write
Table 61:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcRhPortStatus[1:2] register: bit allocation
31
30
29
28
27
26
25
24
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
CSC
0
R/W
8
PPS
0
R/W
0
CCS
0
R/W
reserved
-
-
14
PRSC
0
R/W
12
OCIC
0
R/W
11
PSSC
0
R/W
10
PESC
0
R/W
9
LSDA
0
R/W
1
PES
0
R/W
-
-
-
-
15
13
reserved
-
-
7
-
-
6
-
-
5
-
-
4
-
-
3
-
-
2
reserved
-
-
PRS
0
R/W
POCI
0
R/W
PSS
0
R/W
-
-
-
-
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