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參數(shù)資料
型號: ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 79/150頁
文件大小: 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
79 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.2.2
HcFmRemaining register (R/W: 0EH/8EH)
The HcFmRemaining register is a 14-bit down counter showing the bit time remaining
in the current frame. The bit allocation is given in
Table 49
.
Code (Hex): 0E
read
Code (Hex): 8E
write
Table 48:
Bit
31
HcFmInterval register: bit description
Symbol
Description
FIT
FrameIntervalToggle:
The HCD toggles this bit whenever it loads
a new value to FrameInterval.
FSMPS
[14:0]
Largest Data Packet Counter at the beginning of each frame. The
counter value represents the largest amount of data in bits that can
be sent or received by the HC in a single transaction at any given
time without causing a scheduling overrun. The
fi
eld value is
calculated by the HCD.
-
reserved
FI[13:0]
FrameInterval:
Speci
fi
es the interval between two consecutive
SOFs in bit times. The nominal value is set to 11999. The HCD
must store the current value of this
fi
eld before resetting the HC.
Setting the HostControllerReset (HCR)
fi
eld of the
HcCommandStatus register causes the HC to reset this
fi
eld to its
nominal value. The HCD may choose to restore the stored value
upon completing the Reset sequence.
30 to 16
FSLargestDataPacket:
Speci
fi
es a value that is loaded into the
15 to 14
13 to 0
Table 49:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcFmRemaining register: bit allocation
31
FRT
0
R/W
23
30
29
28
27
26
25
24
reserved
-
-
19
-
-
-
-
-
-
-
-
-
-
-
-
22
21
20
18
17
16
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9
-
-
8
15
14
13
12
11
10
reserved
FR[13:8]
-
-
7
-
-
6
0
0
0
0
0
0
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
FR[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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