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參數資料
| 型號： | LC89052TA-E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO24 |
| 封裝： | 0.225 INCH, TSSOP-24 |
| 文件頁數： | 42/42頁 |
| 文件大小： | 224K |
| 代理商： | LC89052TA-E |
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LC89052TA-E
No.7457-9/42
8. Function Description
8.1 System Reset (
_____
PD)
The system operates normally when
_____
PD pin is set to high level after a supply voltage is rises to 2.7V or higher. When
you set the
_____
PD pin to low again after power is applied, the system is reset.
When power is on, resetting must be done with the
_____
PD pin set to low.
If a crystal oscillator is used, you must wait to start normal operation for at least 10ms until the oscillation gets stable
after the
_____
PD pin goes from low to high.
Figure 8.1
_____
PD Pin Levels at Power On
8.2 Low-Power Modes
The LC89052TA-E supports two low-power modes: the mode in which whole circuit is controlled with the
_____
PD pin
and the mode in which only special functions are controlled by the PDOWN[1:0].
The low-power mode controlled by the
_____
PD applies to the entire circuit of the LC89052TA-E. All clocks are stopped
and the registers are initialized.
The pins that are available with the low-power settings except for the oscillation amplifier are only the XIN pin and
XOUT pin. These can be used to provide the master clock for the DSP and other circuits.
The pins that are available with the PDOWN[1:0] low-power mode settings except those for the oscillator amplifier
and its divider circuit are only the CKOUT, BCK, LRCK, DATAO, SDIN, XIN and XOUT pins. This mode can be
used to minimize power consumption during analog data processing.
When the oscillator amplifier is stopped by the AMPOPR in a low-power mode setup with PDOWN[1:0] or when this
circuit is already stopped, it is impossible for the LC89052TA-E to provide a clock output. Thus the AMPOPR takes
precedence. Note that the PLLOPR setting is invalid and the PLL circuit is stopped.
When the low-power mode is set with PDOWN[1:0], it is possible to write to the microcontroller registers. However,
all the sub-code Q and channel status that are read are fixed at a low level.
VDD
PD
2.7V
t
2.0V
t > 200
System reset
System operation
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