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參數資料
| 型號： | LC89052TA-E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO24 |
| 封裝： | 0.225 INCH, TSSOP-24 |
| 文件頁數： | 5/42頁 |
| 文件大?。?/td> | 224K |
| 代理商： | LC89052TA-E |
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LC89052TA-E
No.7457-13/42
8.3.3 Output clocks (CKOUT, BCK, LRCK)
The clock source for the clocks output from CKOUT, BCK, and LRCK can be selected from two master clocks, the
PLL circuit and the XIN pin.
Normally, when the PLL circuit is locked, the master clock is switched to the PLL source, and when the PLL circuit is
unlocked, the master clock automatically switches to the XIN source. To switch the clock source forcibly, set with
OCKSEL. Clock continuity is maintained when the clock source is selected by the locked/unlocked state of the PLL
circuit or OCKSEL.
Clock switching depends on the PLL circuit locked/unlocked state at the time of the register setup. If the PLL source
is selected with OCKSEL when the PLL circuit is unlocked, the clock is automatically switched after the PLL circuit
is locked.
When VCO operation is stopped with PLLOPR, XIN becomes the clock source. However, clock continuity cannot be
maintained if the operation is stopped with PLLOPR while the PLL circuit is locked. When a low-power mode is set,
continuity cannot be maintained if the mode is switched from the locked PLL.
Table 8.4 Register Settings, PLL States, and the Clock Source
OCKSEL
0
1
PLL state
Locked
Unlocked
Locked
Unlocked
Clock source
PLL
XIN
Either the PLL clock or the XIN clock is output from the CKOUT pin. The divided clock of CKOUT is output from
the BCK pin and LRCK pin.
The PLL lock time frequency is set with PLLCK[1:0]. However, it is possible to maintain clock continuity without
losing the PLL locked state when switching, in the PLL locked state, from the 512fs setting mode with PLLCK[1:0] =
"10" to the (512/2)fs setting with the PLLCK[1:0] = "11", as well as when switching in the reverse direction.
If you use the following procedure to switch between 512fs and (512/2)fs, the BCK and LRCK output clock
continuity can be maintained, and the CKOUT output clock frequency can be held within a narrow band. Other
PLLCK[1:0] switching would result in a lock error.
Figure 8.4 Flowchart for CKOUT Output Clock Narrow Band Operation
Data input
LOCK
detection
fs
calculation
512fs set
PLLCK0=0
PLLCK1=1
PLLCK0=1
PLLCK1=1
No
Yes
fs=96kHz
fs=48kHz
(512/2)fs set
CKOUT output
24.576MHz
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LC89052TA-TLM-E | 功能描述:音頻發送器、接收器、收發器 RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
| LC89052THS-E | 制造商:ON Semiconductor 功能描述:AUDIO I/F RECEIVER |
| LC890561W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory |
| LC890561W-E | 功能描述:音頻發送器、接收器、收發器 RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
| LC89056W-E | 功能描述:音頻發送器、接收器、收發器 RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
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