
WRITING TO THE PAGE RAM
The Display Page RAM can contain up to 512 of the above listed characters and control codes. Each character, or control code
will consume one of the possible 512 locations. For convenience, writing a 1 to bit 3 of the Frame Control Register (0x8400) resets
all page RAM values to zero. This should be done at power up to avoid unpredictable behavior.
Display Window 1 will also start at the first location (corresponding to the I2C address 0x8000). This location must always contain
the Skip-Line (SL) code associated with the first line of Display Window 1. The attribute for this SL code must be written before the
SL code itself, and will be stored in the lower four bits of this memory location. Subsequent locations should contain the characters
to be displayed on line 1 of Display Window 1, until the EOL code or EOS code is written into the Display Page-RAM.
The skip-line parameters associated with the next line must always be written to the location immediately after the preceding line’s
End-of-Line character. The only exception to this rule is when an End-of-Screen character (value 0x0000) is encountered. It is
important to note that an End-of-Line character should not precede an End-of-Screen character (otherwise the End-of-Screen
character will be interpreted as the next line’s skip-line code). Instead, the End-of-Screen code will end the line and also end the
window, making it unnecessary to precede it with an EOL. The I2C Format for writing a sequence of display characters is minimized
by allowing sequential characters with the same attribute code to send in a string as follows:
Byte #1: I2C Slave Address
Byte #2: LSB Register Address
Byte #3: MSB Register Address
Byte #4: Attribute Table Entry to use for the following s skip-line code or characters
Byte #5: First display character, SL parameter, EOL or EOS control code
Byte #6: Second display character, SL parameter, EOL or EOS control code
Byte #7: Third display character, SL parameter, EOL or EOS control code
Byte #n: Last display character in this color sequence, SL parameter, EOL or EOS control code to use the associated Attribute
Table Entry.
This communication protocol is known as the Auto Attribute Mode, which is also used by the LM1237 and LM1247. Please see
examples of usage for this mode in the LM1247 datasheet.
TABLE 14. Sequence of Transmitted Bytes
ENHANCED PAGE RAM ADDRESS MODES
Since the LM1276 is able to support 9-bit character codes, usually two bytes of Page RAM information has to be sent to every
location. To avoid this, the LM1276 addressing control system has 3 additional addressing modes offering increased flexibility that
may be helpful in sending data to the Page RAM. Some of the left over bits in the Attribute byte are employed as data control bits
to select the desired addressing mode as shown in
Table 6. This is identified as the first byte sent in a write operation or the Page
RAM's upper byte read in Table 7.
TABLE 15. Attribute Byte
ATTRIBUTE Byte
X
DC[1]
DC[0]
CC[8]
ATT[3:0]
AUTO ATTRIBUTE MODE
The Auto Attribute mode is the standard LM1247 mode that is described above in the WRITING TO THE PAGE RAM section. The
TABLE 16. Auto Attribute Mode
ATTRIBUTE Byte
X
0
ATT[3:0]
When bits 6–5 are 0, the 9th character code and the 4-bit attribute code will be automatically applied to all the character codes
transmitted after this attribute byte, as in the LM1237 and LM1247. This mode is useful for sending character codes that use the
same attribute, and which are in the same 4 out of 8 banks of the Page ROM. A new transmission must be started to access another
character that is not in the same 4 banks of the Page ROM, and no further attribute codes can follow without stopping and restarting
a new transmission. The Page RAM address is automatically incremented starting with the initial LSB and MSB address in the
beginning of the sequence.
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200969 Version 2 Revision 4
Print Date/Time: 2011/07/11 11:20:12
LM1276