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參數(shù)資料
型號: LM1276AAA/NA
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 音頻/視頻放大
英文描述: 1 CHANNEL, VIDEO PREAMPLIFIER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 38/50頁
文件大小: 6075K
代理商: LM1276AAA/NA
HiBrite Status Register:
STATUS (0x8591)
INTR
RSV
Bits 6–0
Reserved and should be set to zero.
Bits 7
This bit is the interrupt bit and must be frequently polled (at least 480ms interval) by the MCU for a value of 1, and must
be also reset by the MCU thereafter. The interrupt bit will automatically be set high when the software has attempted to
send a command to the MCU, with the chip as the messenger. It must be set back to 0 by the MCU afterwards so that
it can be set high the next time the MCU software makes another attempt to send a command.
MCU Command Register:
MCU COMMAND (0x8592)
MCU COMMAND[7:0]
Bits 7–0
Command. These bits are the MCU command bits. The MCU must read a value of 0x80 from this register.
Sub Command Register:
SUB COMMAND (0x8593)
SUB COMMAND[7:0]
Bits 7–0
Sub Command. These bits are the sub command bits. If a value of this register is
0x01: This value corresponds to a HiBrite Software "UP" command.
0x02: This value corresponds to a HiBrite Software "DOWN" command.
0x01: This value corresponds to a prompt for the MCU to perform a "V Blank Duration Adjustment."
Sequence Number:
SEQ NUM (0x859A)
SEQ NUM[7:0]
Bits 7–0
Sequence. These bits are the Sequence number command bits. The MCU should read this register and take note of
the sequence number to compare with the current sequence number. Since an MCU sub command is continuously
transmitted by the software for a duration of time, the interrupt bit will be set back to high again redundantly, which will
falsely notify the MCU of another sub command. To prevent this, the sequence number which is only updated on truly
new commands, will prevent redundant commands and have the the MCU set the interrupt but low accordingly.
Please see the "MCU Programmer's Guide" Applications note on more detailed information regarding the use of registers 0x8590
- 0x859A.
Internal PLL Lock Detect Control Register:
STATUS (0xFFF8)
RSV
LOCK
SET
LOCK
ORR
RSV
Bits 3–0
Reserved and should be set to zero.
Bits 5-4
When enabling the OSD display, these 2 bits must be enabled first, and then disabled when the OSD display is disabled.
This should also be done before performing an auto size calculation.
Bits 7-6
Reserved and should be set to zero.
H INPUT SEL (0xFFFD)
RSV
HSEL
RSV
43
www.national.com
200969 Version 2 Revision 4
Print Date/Time: 2011/07/11 11:20:12
LM1276
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PDF描述
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