
Operating Descriptions
(Continued)
tion section, when the duty cycle D1 for Channel 1 overlaps
the duty cycle D2 for Channel 2, the input rms current
increases, requiring more input capacitors or input capaci-
tors with higher ripple current ratings. The new, reduced
maximum duty cycle can be calculated by multiplying the
sync frequency (in Hz) by 2.5x10
-6
(the fixed delay in sec-
onds).
D
MAX
= FSYNC
*
2.5x10
-6
(5)
At a sync frequency of 150kHz, for example, the maximum
duty cycle for Channel 1 that will not overlap Channel 2
would be 37.5%. At 250kHz, it is the duty cycle for Channel
2 that is reduced to a D
MAX
of 37.5%.
Component Selection
OUTPUT VOLTAGE SETTING
The output voltage for each channel is set by the ratio of a
voltage divider as shown in
Figure 9
. The resistor values can
be determined by the following equation:
(6)
Where Vfb=1.238V. Although increasing the value of R1 and
R2 will increase efficiency, this will also decrease accuracy.
Therefore, a maximum value is recommended for R2 in
order to keep the output within .3% of Vnom. This maximum
R2 value should be calculated first with the following equa-
tion:
(7)
Where 200nA is the maximum current drawn by FBx pin.
Example: Vnom=5V, Vfb=1.2364V, Ifbmax=200nA.
(8)
Choose 60K
(9)
The Cycle Skip and Dropout modes of the LM5642 IC regu-
late the minimum and maximum output voltage/duty cycle
that the converter can deliver. Both modes check the voltage
at the COMP pin. Minimum output voltage is determined by
the Cycle Skip Comparator. This circuitry skips the high side
FET ON pulse when the COMP pin voltage is below 0.5V at
the beginning of a cycle. The converter will continue to skip
every other pulse until the duty cycle (and COMP pin volt-
age) rise above 0.5V, effectively halving the switching fre-
quency.
Maximum output voltage is determined by the Dropout cir-
cuitry, which skips the low side FET ON pulse whenever the
COMP pin voltage exceeds the ramp voltage derived from
the current sense. Up to three low side pulses may be
skipped in a row before a minimum duty pulse must be
applied to the low side FET.
Figure 10
shows the range of ouput voltage (for Io = 3A) with
respect to input voltage that will keep the converter from
entering either Skip Cycle or Dropout mode.
For input voltages below 5.5V, VLIN5 must be connected to
Vin through a small resistor (approximately 4.7 ohm). This
will ensure that VLIN5 does not fall below the UVLO thresh-
old.
20060180
(a)
20060181
(b)
20060182
(c)
FIGURE 8.
20060111
FIGURE 9. Output Voltage Setting
L
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