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參數資料
| 型號： | MAX5952CUAX+ |
| 廠商： | Maxim Integrated |
| 文件頁數： | 17/50頁 |
| 文件大?。?/td> | 1006K |
| 描述： | IC PSE CNTRLR FOR POE 36-SSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 30 |
| 類型： | 以太網供電控制器（PoE） |
| 應用： | 遠程外設（工業控制，相機，數據訪問） |
| 內部開關： | 無 |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-BSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 36-SSOP |
| 包裝： | 管件 |
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High-Power, Quad, PSE Controller
for Power-Over-Ethernet
______________________________________________________________________________________ 17
A valid PD has a 25k& discovery signature characteristic
as specified in the IEEE 802.3af/at standard. Table 1
shows the IEEE 802.3af/at specification for a PSE detect-
ing a valid PD signature. See the Typical Operating
Circuits and Figure 1 (Detection, Classification, and
Power-Up Port Sequence). The MAX5952 can probe and
categorize different types of devices connected to the
port such as: a valid PD, an open circuit, a low resistive
load, a high resistive load, a high capacitive load, a posi-
tive DC supply, or a negative DC supply.
During detection, the MAX5952 keeps the external
MOSFET off and forces two probe voltages through the
DET_ input. The current through the DET_ input is mea-
sured as well as the voltage at OUT_. A two-point slope
measurement is used as specified by the IEEE 802.3af
standard to verify the device connected to the port. The
MAX5952 implements appropriate settling times and a
100ms digital integration to reject 50Hz/60Hz power-
line noise coupling.
An external diode, in series with the DET_ input,
restricts PD detection to the first quadrant as specified
by the IEEE 802.3af/at standard. To prevent damage to
non-PD devices, and to protect itself from an output
short circuit, the MAX5952 limits the current into DET_
to less than 2mA maximum during PD detection.
In midspan mode, the MAX5952 waits 2.2s before
attempting another detection cycle after every failed
detection. The first detection, however, happens imme-
diately after issuing the detection command.
High-Capacitance Detection
The CLC_EN bit in register R23h[5] enables the large
capacitor detection feature for legacy PD devices.
When CLC_EN = 1, the high-capacitance detection limit
is extended up to 100礔. CLC_EN = 0 is the default
condition for the normal capacitor size detection. See
Table 1 and the Register Map and Description section.
Table 1. PSE PI Detection Modes Electrical Requirement
(Table 33-2 of the IEEE 802.3af Standard)
PARAMETER
SYMBOL
MIN
MAX
UNITS
ADDITIONAL INFORMATION
Open-Circuit Voltage
V
OC
30
V
In detection mode only
Short-Circuit Current
I
SC
5
mA
In detection mode only
Valid Test Voltage
V
VALID
2.8
10
V
Voltage Difference
Between Test Points
V
TEST
1
V
Time Between Any Two
Test Points
t
BP
2
ms
This timing implies a 500Hz maximum probing
frequency
Slew Rate
V
SLEW
0.1
V/祍
Accept Signature
Resistance
R
GOOD
19
26.5
k&
Reject Signature
Resistance
R
BAD
< 15
> 33
k&
Open-Circuit Resistance
R
OPEN
500
k&
Accept Signature
Capacitance
C
GOOD
150
nF
Reject Signature
Capacitance
C
BAD
10
礔
Signature Offset Voltage
Tolerance
V
OS
0
2.0
V
Signature Offset Current
Tolerance
I
OS
0
12
礎
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MAX5952CUAX+ | 功能描述:熱插拔功率分布 Quad PSE Controller for POE RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5952CUAX+T | 功能描述:熱插拔功率分布 Quad PSE Controller for POE RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5952DEAX+ | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| MAX5952DEAX+T | 制造商:Maxim Integrated Products 功能描述:HIGH-POWER QUAD PSE CONTROLLER FOR - Tape and Reel |
| MAX5952DUAX+ | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
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