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參數(shù)資料
型號(hào): MAX5952CUAX+
廠商: Maxim Integrated
文件頁(yè)數(shù): 33/50頁(yè)
文件大小: 1006K
描述: IC PSE CNTRLR FOR POE 36-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
類型: 以太網(wǎng)供電控制器(PoE)
應(yīng)用: 遠(yuǎn)程外設(shè)(工業(yè)控制,相機(jī),數(shù)據(jù)訪問(wèn))
內(nèi)部開關(guān): 無(wú)
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-BSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 36-SSOP
包裝: 管件
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
______________________________________________________________________________________   33
Setting DET_EN_/CLASS_EN_ to 1 (Table 18) enables
load detection/classification, respectively. Detection
always has priority over classification. To perform clas-
sification without detection, set the DET_EN_ bit low
and CLASS_EN_ bit high.
In manual mode, R14h works like a pushbutton. Set the
bits high to begin the corresponding routine. The bit
clears after the routine finishes.
When entering auto mode, R14h defaults to FFh. When
entering semi or manual modes, R14h defaults to 00h.
A reset or power-up sets R14h = AAAAAAAAb where A
represents the latched-in state of the AUTO input prior
to the reset.
Table 18. Detection and Classification Enable Register
ADDRESS = 14h
SYMBOL
BIT
R/W
DESCRIPTION
CLASS_EN4
7
R/W
Enable classification on port 4
CLASS_EN3
6
R/W
Enable classification on port 3
CLASS_EN4
5
R/W
Enable classification on port 2
CLASS_EN3
4
R/W
Enable classification on port 1
DET_EN4
3
R/W
Enable detection on port 4
DET_EN3
2
R/W
Enable detection on port 3
DET_EN2
1
R/W
Enable detection on port 2
DET_EN1
0
R/W
Enable detection on port 1
Table 19. Backoff and High-Power Enable Register
ADDRESS = 15h
SYMBOL
BIT
R/W
DESCRIPTION
BCKOFF4
3
R/W
Enable cadence timing on port 4
BCKOFF3
2
R/W
Enable cadence timing on port 3
BCKOFF2
1
R/W
Enable cadence timing on port 2
BCKOFF1
0
R/W
Enable cadence timing on port 1
CL_DISC (R17h[2]) and ENx_CL6 (R1Ch[7:4]) are used
to program the high-power mode. See Table 3 for details.
Setting BCKOFF_ to 1 (Table 19) enables cadence tim-
ing on each port where the port backs off and waits
2.2s after each failed load discovery detection. The
IEEE 802.3af standard requires a PSE that delivers
power through the spare pairs (midspan PSE) to have
cadence timing.
A reset or power-up sets R15h = 0000XXXXb where X
is the logic AND of the MIDSPAN and AUTO inputs.
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