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參數資料
型號: MAX5952CUAX+
廠商: Maxim Integrated
文件頁數: 38/50頁
文件大小: 1006K
描述: IC PSE CNTRLR FOR POE 36-SSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 30
類型: 以太網供電控制器(PoE)
應用: 遠程外設(工業控制,相機,數據訪問)
內部開關:
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-BSOP(0.295",7.50mm 寬)
供應商設備封裝: 36-SSOP
包裝: 管件
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
38   ______________________________________________________________________________________
The CLC_EN enables the large capacitor detection fea-
ture. When CLC_EN is set the device can recognize a
capacitor load up to 100礔. If the CLC_EN is reset, the
MAX5952 performs normal detection.
AC_TH allows programming of the threshold of the AC
disconnect comparator. The threshold is defined as a
current since the comparators verify that the peak of
the current pulses sensed at the DET_ input exceed a
preset threshold. The current threshold is defined as
follows:
IAC_TH = 226.68礎 + 28.33 x NAC_TH
where NAC_TH is the decimal value of AC_TH.
When set low, DET_BY inhibits port power-on if the dis-
covery detection was bypassed in auto mode. When
set high, DET_BY allows the device to turn on power to
a non-IEEE 802.3af load without doing detection. If
OSCF_RS is set high, the OSC_FAIL bit is ignored. A
reset or power-up sets R23h = 04h. Default IAC_TH is
340礎.
Table 27. Switch Mode Register
ADDRESS = 1Fh
SYMBOL
BIT
R/W
DESCRIPTION
EN_WHDOG
7
R/W
A logic-high enables the watchdog function
WD_INT_EN
6
R/W
Enables interrupt on SMODE_ bits
Reserved
5

Reserved
Reserved
4
R/W
Reserved
HWMODE4
3
R/W
Port 4 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer
expires
HWMODE3
2
R/W
Port 3 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer
expires
HWMODE2
1
R/W
Port 2 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer
expires
HWMODE1
0
R/W
Port 1 switches to AUTO if logic-high and to SHUTDOWN if logic-low when watchdog timer
expires
Table 28. Program Register
ADDRESS = 23h
SYMBOL
BIT
R/W
DESCRIPTION
Reserved
7

Reserved
Reserved
6

Reserved
CLC_EN
5
R/W
Large capacitor detection enable
DET_BY
4
R/W
Enables skipping detection in AUTO mode
OSCF_RS
3
R/W
OSC_FAIL reset bit
2
R/W
AC_TH[2]
1
R/W
AC_TH[1]
AC_TH
0
R/W
AC_TH[0]
Setting EN_WHDOG (Table 27) high activates the
watchdog counter. When the counter reaches zero, the
port switches to the hardware-controlled mode deter-
mined by the corresponding HWMODE_ bit. A low in
HWMODE_ switches the port into shutdown by setting
the bits in register R12h to 00. A high in HWMODE_
switches the port into auto mode by setting the bits in
register R12h to 11. If WD_INT_EN is set, an interrupt is
sent if any of the SMODE bits are set. A reset sets R1Fh
= 00h.
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