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參數資料
型號: MC68HC05BD5
廠商: Motorola, Inc.
英文描述: 8-Bit Microcontroller Units (MCU).(8位微控制器)
中文描述: 8位微控制器單元(MCU)。(8位微控制器)
文件頁數: 34/112頁
文件大小: 676K
代理商: MC68HC05BD5
MOTOROLA
4-2
MC68HC05BD3
RESETS AND INTERRUPTS
4
4.1.3
Illegal Address (ILADR) Reset
The MCU monitors all opcode fetches. If an illegal address space is accessed during an opcode
fetch, an internal reset is generated. Illegal address spaces consist of all unused locations within
the memory map and the I/O registers (see Figure 3-1). Because the internal reset signal is used,
the MCU comes out of an ILADR reset in the same operating mode it was in when the opcode was
fetched.
4.1.4
Computer Operating Properly (COP) Reset
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a
specific amount of time by a program reset sequence.
Figure 4-1
Power-On Reset and RESET Timing
VDD
XTAL PIN
1
INTERNAL
CLOCK
2
INTERNAL
ADDRESS
BUS
2
INTERNAL
DATA
BUS
2
RESET
3FFE
3FFF
NEW PC
3FFE
3FFE
3FFF
t
VDDR
VDD THRESHOLD (TYPICALLY 1-2V)
4064 t
cyc
t
oxov
t
cyc
3
NEW
PCH
NEW
PCL
OP
CODE
t
RL
=1.5t
CYC
PCH
PCL
OP
CODE
NEW PC
NOTES:
1. XTAL is not meant to represent frequency. It is only used to represent time.
2. Internal clock, internal address bus, and internal data bus signals are not available externally.
3. Next rising edge of internal clock after rising edge of RESET initiates reset sequence.
TPG
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