
MC68HC05BD3
MOTOROLA
8-9
SYNC SIGNAL PROCESSOR
8
8.3.2
Vertical Frequency Registers (VFRS)
This 13-bit read only register pair contains information of the vertical frame frequency. An internal
counter counts the number of internal clocks between two VSYNC pulses. The counted value will
then be transferred to this register. The data corresponds to the period of one vertical frame. This
register can be read to determine if the frame frequency is valid, and to determine the video mode.
However, the data is not valid if VDET bit is cleared.
The frame frequency is calculated by 1/(VFR
±
1 x 8
μ
s) or 1/(VFR
±
1 x 16t
CYC
).
The table below shows examples for the Vertical Frequency Register, all VFR numbers are in
hexadecimal
.
8.3.3
Line Frequency Registers (LFRs)
This 12-bit read only register pair contains the number of horizontal lines in each vertical frame.
An internal line counter counts the horizontal sync pulses between two vertical sync pulses. The
counted value will be transferred to this register pair. HOVER bit will be set if the incoming
horizontal sync pulses between two vertical sync pulses are more than 4096 or there is no vertical
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
VFHR
$000D
VF12
VF11
VF10
VF9
VF8
0000 0000
VFLR
$000E
VF7
VF6
VF5
VF4
VF3
VF2
VF1
VF0
0000 0000
Table 8-1
Vertical Frame Frequencies
VFR
$03C0
$03C1
$03C2
$04E2
$04E3
$04E4
$06F9
$06FA
$06FB
Min. Freq.
130.07
129.94
129.80
99.92
99.84
99.76
69.99
69.95
69.91
Max. Freq.
130.34
130.21
130.07
100.08
100.00
99.92
70.07
70.03
69.99
VFR
$0823
$0824
$0825
$09C4
$09C5
$09C6
$1FFD
$1FFE
$1FFF
Min. Freq.
59.98
59.95
59.92
49.98
49.96
49.94
15.262
15.260
15.258
Max. Freq.
60.04
60.01
59.98
50.02
50.00
49.98
15.266
15.264
15.262
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
LFHR
$000F HOVER
LF11
LF10
LF9
LF8
0000 0000
LFLR
$0010
LF7
LF6
LF5
LF4
LF3
LF2
LF1
LF0
0000 0000
TPG