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參數(shù)資料
| 型號： | MC68HC05BD5 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 42/112頁 |
| 文件大小： | 676K |
| 代理商： | MC68HC05BD5 |
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MOTOROLA
5-2
MC68HC05BD3
MULTI-FUNCTION TIMER
5
This bit is set when the 8-bit ripple counter overflows from $FF to $00; a timer overflow interrupt
will occur, if TOFIE (bit 5) is set. TOF is cleared by writing a “0” to the bit.
RTIF - Real Time Interrupt Flag
1 (set)
–
A real time interrupt has occurred.
0 (clear) –
A real time interrupt has not occurred.
When RTIF is set, a CPU interrupt request is generated if RITE is set. The clock frequency that
drives the RTI circuit is E/16384 giving a maximum interrupt period of 8.19ms at a bus rate of
2MHz. RTIF is cleared by writing a “0” to the bit.
TOFIE - Timer Overflow Interrupt Enable
1 (set)
–
TOF interrupt is enabled.
0 (clear) –
TOF interrupt is disabled.
RTIE - Real Time Interrupt Enable
1 (set)
–
Real time interrupt is enabled.
0 (clear) –
Real time interrupt is disabled.
IRQN - IRQ Pin Trigger Option
1 (set)
–
Negative edge triggering for IRQ only
0 (clear) –
Level and negative edge triggering for IRQ
RT1, RT0 - Rate Select for COP watchdog and RTI
See Section 5.3 on watchdog reset.
5.3
COP Watchdog
The COP (Computer Operating Properly) watchdog timer function is implemented by using the
output of the Multi-Function Timer counter. The minimum COP reset rates are controlled by RT0
and RT1 of MFT Control and Status register. If the COP circuit times out, an internal reset is
generated and the reset vector is fetched (at $3FFE & $3FFF). Preventing a COP time-out is
achieved by writing a “0” to bit 0 of address $3FF0. The COP counter has to be cleared periodically
by software with a period less than COP reset rate. The COP watchdog timer is always enabled
and continues to count in Wait mode.
TPG
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