
List of Figures
MC68HC08AB16A
—
Rev. 2.0
Technical Data
MOTOROLA
List of Figures
23
Figure
Title
Page
11-4
11-5
11-6
11-7
11-8
11-9
11-10 TIMA Channel 1 Status and Control Register (TASC1) . . . . .180
11-11 TIMA Channel 2 Status and Control Register (TASC2) . . . . .181
11-12 TIMA Channel 3 Status and Control Register (TASC3) . . . . .181
11-13 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
11-14 TIMA Channel 0 Register High (TACH0H). . . . . . . . . . . . . . .184
11-15 TIMA Channel 0 Register Low (TACH0L). . . . . . . . . . . . . . . .184
11-16 TIMA Channel 1 Register High (TACH1H). . . . . . . . . . . . . . .185
11-17 TIMA Channel 1 Register Low (TACH1L). . . . . . . . . . . . . . . .185
11-18 TIMA Channel 2 Register High (TACH2H). . . . . . . . . . . . . . .185
11-19 TIMA Channel 2 Register Low (TACH2L). . . . . . . . . . . . . . . .185
11-20 TIMA Channel 3 Register High (TACH3H). . . . . . . . . . . . . . .186
11-21 TIMA Channel 3 Register Low (TACH3L). . . . . . . . . . . . . . . .186
TIMA Status and Control Register (TASC). . . . . . . . . . . . . . .176
TIMA Counter Register High (TACNTH). . . . . . . . . . . . . . . . .178
TIMA Counter Register Low (TACNTL) . . . . . . . . . . . . . . . . .179
TIMA Counter Modulo Register High (TAMODH). . . . . . . . . .179
TIMA Counter Modulo Register Low (TAMODL) . . . . . . . . . .179
TIMA Channel 0 Status and Control Register (TASC0) . . . . .180
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10 TIMB Channel 1 Status and Control Register (TBSC1) . . . . .206
12-11 TIMB Channel 2 Status and Control Register (TBSC2) . . . . .207
12-12 TIMB Channel 3 Status and Control Register (TBSC3) . . . . .207
12-13 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
12-14 TIMB Channel 0 Register High (TBCH0H). . . . . . . . . . . . . . .210
12-15 TIMB Channel 0 Register Low (TBCH0L). . . . . . . . . . . . . . . .210
12-16 TIMB Channel 1 Register High (TBCH1H). . . . . . . . . . . . . . .211
12-17 TIMB Channel 1 Register Low (TBCH1L). . . . . . . . . . . . . . . .211
TIMB Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
TIMB I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .191
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .195
TIMB Status and Control Register (TBSC). . . . . . . . . . . . . . .202
TIMB Counter Register High (TBCNTH). . . . . . . . . . . . . . . . .204
TIMB Counter Register Low (TBCNTL) . . . . . . . . . . . . . . . . .205
TIMB Counter Modulo Register High (TBMODH). . . . . . . . . .205
TIMB Counter Modulo Register Low (TBMODL) . . . . . . . . . .205
TIMB Channel 0 Status and Control Register (TBSC0) . . . . .206