
MC68HC16R1/916R1
USER’S MANUAL
SINGLE-CHIP INTEGRATION MODULE 2
MOTOROLA
5-21
The following equation calculates the PIT period for an externally input clock
frequency on both slow and fast reference frequency devices.
5.4.7 Interrupt Priority and Vectoring
Interrupt priority and vectoring are determined by the values of the periodic interrupt
request level (PIRQL[2:0]) and periodic interrupt vector (PIV) fields in the periodic
interrupt control register (PICR).
The PIRQL field is compared to the CPU16 interrupt priority mask to determine
whether the interrupt is recognized.
Table 5-8
shows PIRQL[2:0] priority values. Be-
cause of SCIM2 hardware prioritization, a PIT interrupt is serviced before an external
interrupt request of the same priority. The periodic timer continues to run when the in-
terrupt is disabled.
The PIV field contains the periodic interrupt vector. The vector is placed on the IMB
when an interrupt request is made. The vector number is used to calculate the address
of the appropriate exception vector in the exception vector table. The reset value of
the PIV field is $0F, which corresponds to the uninitialized interrupt exception vector.
5.4.8 Low-Power STOP Operation
When the CPU16 executes the LPSTOP instruction, the current interrupt priority mask
is stored in the clock control logic, internal clocks are disabled according to the state
of the STSCIM bit in the SYNCR, and the MCU enters low-power stop mode. The bus
monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power
stop.
During low-power stop mode, the clock input to the software watchdog timer is dis-
abled and the timer stops. The software watchdog begins to run again on the first rising
clock edge after low-power stop mode ends. The watchdog is not reset by low-power
stop mode. A service sequence must be performed to reset the timer.
Table 5-8 Periodic Interrupt Priority
PIRQL[2:0]
000
001
010
011
100
101
110
111
Priority Level
Periodic Interrupt Disabled
Interrupt priority level 1
Interrupt priority level 2
Interrupt priority level 3
Interrupt priority level 4
Interrupt priority level 5
Interrupt priority level 6
Interrupt priority level 7
PIT Period
PITM[7:0]
---------------------------------------------------------------------------------------------------------------------
(
)
1 if PTP = 0, 512 if PTP = 1
(
f
ref
)
4
( )
=