
MC68HC16R1/916R1
USER’S MANUAL
OVERVIEW
MOTOROLA
3-11
Table 3-3
summarizes pin functions of the MC68HC16R1 and MC68HC916R1 MCUs.
Entries in the “Active State(s)” column denote the polarity of each MCU pin in its active
state. Some MCU pins have multiple functions and thus have multiple entries in the
“Active State(s)” column. For example, the ADDR23/CS10/ECLK pin can be pro-
grammed to be either address line 23 (ADDR23), chip-select output 10 (CS10), or the
M6800 bus clock (ECLK). Its entry in the “Active State(s)” column is “—/0/—” which
indicates the following:
When programmed as ADDR23, the pin has no active state (“—”); it conveys in-
formation when driven by the MCU to logic 0 or logic 1.
When programmed as CS10, the pin is active when driven to logic 0 (“0”) by the
MCU. When driven to logic 1, the chip select function is inactive.
When programmed as ECLK, the pin has no active state (“—”). M6800 bus de-
vices drive or prepare to latch an address when ECLK is logic 0 and drive or pre-
pare to latch data when ECLK is logic 1.
The “Discrete I/O Use” column indicates whether each pin can be used as a general
purpose input, output, or both. Those pins that cannot be used for general purpose I/
O will have a “—” in this column.
NOTES:
1. AN[7:0]/PADA[7:0], FASTREF/PF0, MISO/PMC0, MOSI/PMC1, SCK/PMC2, SS/PMC3, RXDB/PMC4, TXDB/
PMC5, RXDA/PMC6, and TXDA/PMC7 inputs are only synchronized when used as discrete general purpose
inputs.
2. BERR is only synchronized when executing retry or late bus cycle operations. HALT is only synchronized when
executing retry or single-step bus cycle operations. These uses of HALT and BERR are only supported on the
CPU32 and not the CPU16.
3. DATA[15:8]/PG[7:0] and DATA[7:0]/PH[7:0] are only synchronized during reset and when being used as discrete
general purpose inputs.
V
STBY
XFC
XTAL
56
SRAM
—
—
—
62
57
SCIM2
SCIM2
—
—
—
—
—
—
Table 3-2 MC68HC16R1/916R1 Driver Types
Type
A
Aw
I/O
O
O
Description
Three-state capable output signals
Type A output with weak p-channel pullup during reset
Three-state output that includes circuitry to pull up output before high impedance is established,
to ensure rapid rise time
Type B output that can be operated in an open-drain mode
B
O
Bo
O
Table 3-1 MC68HC16R1/MC68HC916R1 Pin Characteristics
Pin
Mnemonic(s)
Pin
Number(s)
Associated
Module
Driver
Type
Synchronized
Input
Input
Hysteresis