
MOTOROLA
6-2
STANDBY RAM MODULE
MC68HC16R1/916R1
USER’S MANUAL
6.3 SRAM Array Address Space Type
The RASP[1:0] in RAMMCR determine the SRAM array address space type. The
SRAM module can respond to both program and data space accesses or to program
space accesses only. Because the CPU16 operates in supervisor mode only, RASP1
has no effect.
Table 6-1
shows RASP[1:0] encodings.
Refer to
5.5.1.7 Function Codes
for more information concerning address space
types and program/data space access. Refer to
4.6 Addressing Modes
for more in-
formation on addressing modes.
6.4 Normal Access
The array can be accessed by byte, word, or long word. A byte or aligned word access
takes one bus cycle or two system clocks. A long word or misaligned word access re-
quires two bus cycles. Refer to
5.6 Bus Operation
for more information concerning
access times.
6.5 Standby and Low-Power Stop Operation
Standby and low-power modes should not be confused. Standby mode maintains the
RAM array when the main MCU power supply is turned off. Low-power stop mode al-
lows the CPU16 to control MCU power consumption by disabling unused modules.
Relative voltage levels of the MCU V
DD
and V
STBY
pins determine whether the SRAM
is in standby mode. SRAM circuitry switches to the standby power source when V
DD
drops below specified limits. If specified standby supply voltage levels are maintained
during the transition, there is no loss of memory when switching occurs. The RAM ar-
ray cannot be accessed while the SRAM module is powered from V
STBY
. If standby
operation is not desired, connect the V
STBY
pin to V
SS
.
I
SB
(SRAM standby current) values may vary while V
DD
transitions occur. Refer to
AP-
PENDIX A ELECTRICAL CHARACTERISTICS
for standby switching and power con-
sumption specifications.
6.6 Reset
Reset places the SRAM in low-power stop mode, enables program space access, and
clears the base address registers and the register lock bit. These actions make it pos-
sible to write a new base address into the ROMBAH and ROMBAL registers.
When a synchronous reset occurs while a byte or word SRAM access is in progress,
the access is completed. If reset occurs during the first word access of a long-word
operation, only the first word access is completed. If reset occurs during the second
word access of a long-word operation, the entire access is completed. Data being read
Table 6-1 SRAM Array Address Space Type
RASP[1:0]
X0
X1
Space
Program and data accesses
Program access only