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參數資料
| 型號： | NCN6001DTBEVB |
| 廠商： | ON Semiconductor |
| 文件頁數： | 3/36頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR NCN6001DTB |
| 設計資源： | NCN6001DTBEVB Gerber Files NCN6001 Demo Brd Schematic NCN6001DBEVB BOM |
| 標準包裝： | 1 |
| 主要目的： | 接口，智能卡 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | NCN6001 |
| 主要屬性： | 與 ISO 7816-3，EMV，GIE-CB 兼容 |
| 次要屬性： | 符合 GSM 規定 |
| 已供物品： | 板 |
| 其它名稱： | NCN6001DTBEVBOS |
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NCN6001
http://onsemi.com
11
PROGRAMMING
Write Register " WRT_REG
The WRT_REG register handles three command bits
[b5:b7] and five data bits [b0:b4] as depicted in Table 1.
These bits are concatenated into a single byte to accelerate
the programming sequence. The register can be updated
when CS is low only.
The CRD_RST pin reflects the content of the MOSI
WRT_REG[b4] during the chip programming sequence.
Since this bit shall be Low to address the internal register of
the chip, care must be observed as this signal will be
immediately transferred to the CRD_RST pin.
Table 1. WRT_REG BITS DEFINITIONS
b0
b1
If (b7 + b6 + b5) <> 110 and (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 111 then
Case 00
CRD_VCC = 0 V
Case 01
CRD_VCC = 1.8 V
Case 10
CRD_VCC = 3.0 V
Case 11
CRD_VCC = 5.0 V
Else if (b7 + b6 + b5) = 110 then
b1 drives C4
b0 drives C8
Else if (b7 + b6 + b5) = 101 then
Case (b4 + b3 + b2 + b1 + b0) = 0000
CRD_DET = NO
Case (b4 + b3 + b2 + b1 + b0) = 0001
CRD_DET = NC
Case (b4 + b3 + b2 + b1 + b0) = 0010
SPI_MODE = Special
Case (b4 + b3 + b2 + b1 + b0) = 0011
SPI_MODE = Normal
End if
b2
b3
If (b7 + b6 + b5) <> 110 and (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 111 then
Case 00
CRD_CLK = L
Case 01
CRD_CLK = CLK_IN
Case 10
CRD_CLK = CLK_IN/2
Case 11
CRD_CLK = CLK_IN/4
Else if (b7 + b6 + b5) = 110 then
b3 drives CRD_CLK
b2 drives CRD_IO
Else if (b7 + b6 + b5) = 101 then
Case (b4 + b3 + b2 + b1 + b0) = 0000
CRD_DET = NO
Case (b4 + b3 + b2 + b1 + b0) = 0001
CRD_DET = NC
Case (b4 + b3 + b2 + b1 + b0) = 0010
SPI_MODE = Special
Case (b4 + b3 + b2 + b1 + b0) = 0011
SPI_MODE = Normal
End if
b4
Drives CRD_RST pin (Note 10)
b5,
b6,
b7
000
Select Asynchronous Card #0 (Note 9), four chips bank CS signal
001
Select Asynchronous Card #1 (Note 9), four chips bank CS signal
010
Select Asynchronous Card #2 (Note 9), four chips bank CS signal
011
Select Asynchronous Card #3 (Note 9), four chips bank CS signal
100
Select External Asynchronous Card, dedicated CS signal
110
Select External Synchronous Card, dedicated CS signal
101
Set Card Detection Switch polarity, Set SPI_MODE normal or special. Set CRD_CLK slopes Fast or Slow.
111
Reserved for future use
9. When operating in Asynchronous mode, [b5:b7] are compared with the external voltage levels present pins C4/S0 and C8/S1 (respectively
pins 15 and 14).
10.The CRD_RST pin reflects the content of the MOSI WRT_REG[b4] during the chip programming sequence. Since this bit shall be Low to
address the internal register of the chip, care must be observed as this signal will be immediately transferred to the CRD_RST pin.
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