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參數資料
| 型號： | NCN6001DTBEVB |
| 廠商： | ON Semiconductor |
| 文件頁數： | 27/36頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR NCN6001DTB |
| 設計資源： | NCN6001DTBEVB Gerber Files NCN6001 Demo Brd Schematic NCN6001DBEVB BOM |
| 標準包裝： | 1 |
| 主要目的： | 接口，智能卡 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | NCN6001 |
| 主要屬性： | 與 ISO 7816-3，EMV，GIE-CB 兼容 |
| 次要屬性： | 符合 GSM 規定 |
| 已供物品： | 板 |
| 其它名稱： | NCN6001DTBEVBOS |
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NCN6001
http://onsemi.com
33
Table of Contents
COMPACT SMART CARD INTERFACE IC
.......
MAXIMUM RATINGS
6
.........................
DIGITAL PARAMETERS SECTION
..............
POWER SUPPLY SECTION
....................
SMART CARD INTERFACE SECTION
..........
PROGRAMMING
.............................
STARTUP DEFAULT CONDITIONS
............
CARD DETECTION
..........................
CRD_VCC OPERATION
......................
POWERUP SEQUENCE
......................
POWER DOWN SEQUENCE
..................
DATA I/O LEVEL SHIFTER
...................
GENERAL PURPOSE CRD_C4 and CRD_C8
.....
INTERRUPT
................................
SPI PORT
...................................
DC/DC OPERATION
.........................
SMART CARD CLOCK DIVIDER
..............
INPUT SHITTY TRIGGERS
...................
SECURITY FEATURES
.......................
ESD PROTECTION
..........................
PRINTED CIRCUIT BOARD LAY OUT
.........
TEST BOARD SCHEMATIC DIAGRAM
.........
ABBREVIATIONS
...........................
DIMENSIONS
...............................
Figures Index
Figure 1. Pin Connections
.......................
Figure 2. Typical Application
....................
Figure 3. Block Diagram
........................
Figure 4. Typical Startup CRD_VCC Sequence
.....
Figure 5. CRD_VCC Typical Rise and Fall Time
....
Figure 6. Startup Sequence with ATR
.............
Figure 7. Typical Power Down Sequence
..........
Figure 8. Basic I/O Internal Circuit
...............
Figure 9. Typical I/O Rise and Fall Time
..........
Figure 10. Typical CRD_C4 Output Drive and Logic
Control
.....................................
Figure 11. Basic Interrupt Function
...............
Figure 12. Basic SPI Timings and Protocol
.........
Figure 13. Chip Address Decoding Protocol and MISO
Sequence
...................................
Figure 14. Basic Multi Command SPI Bytes
........
Figure 15. Programming Sequence, Chip Address = $03
............................................
Figure 16. MISO Read Out Sequences
............
Figure 17. Basic DC/DC Converter
...............
Figure 18. Theoretical DC/DC Operating Waveforms
............................................
Figure 19. Typical CRD_VCC Ripple Voltage
......
Figure 20. CRD_VCC Efficiency as a Function of the
Input Supply Voltage
..........................
Figure 21. CRD_VCC Efficiency as a Function of the
Input Supply Voltage
..........................
Figure 22. Typical Inductor Current
..............
Figure 23. Output Current Limits
................
Figure 24. Output Current Limit as a Function of the
Temperature
.................................
Figure 25. Typical Clock Divider Synchronization
...
Figure 26. Basic Clock Divider and Level Shifter
....
Figure 27. Force CRD_CLK to Low
..............
Figure 28. Force CRD_CLK to Active Mode
.......
Figure 29. CRD_CLK Programming
..............
Figure 30. CRD_CLK Operating Low Speed (Top Trace),
Full Speed (Bottom Trace)
......................
Figure 31. Typical Schmitt Trigger Characteristic
....
Figure 32. NCN6001 Engineering Test Board Schematic
Diagram
....................................
Figure 33. NCN6001 Demo Board Printed Circuit Board
Layout
.....................................
Figure 34. Typical Multiple Parallel Interfaces
......
Tables Index
DIGITAL PARAMETERS
......................
POWER SUPPLY.
.............................
SMART CARD INTERFACE.
..................
Table 1. WRT_REG Bits Definitions
...............
Table 2. WRT_REG Bits Definitions and Functions
..
Table 3. MOSI and MISO Bits Identifications and
Functions
...................................
Table 4. Startup Default Conditions
...............
Table 5. CRD_VCC Output Voltage Range
.........
Table 6. I/O Pullup Resistor True Table
...........
Table 7. Interrupt Reset Logic
...................
Table 8. Interrupt Reset Logic Operation
..........
Table 9. Ceramic/Electrolytic Capacitors Comparison
............................................
Table 10. Output Clock Rise and Fall Time Selection
............................................
Table 11. Demo Board Bill of Material
............
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