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參數(shù)資料
型號: NCN6001DTBEVB
廠商: ON Semiconductor
文件頁數(shù): 5/36頁
文件大小: 0K
描述: EVAL BOARD FOR NCN6001DTB
設計資源: NCN6001DTBEVB Gerber Files
NCN6001 Demo Brd Schematic
NCN6001DBEVB BOM
標準包裝: 1
主要目的: 接口,智能卡
嵌入式: 是,MCU,8 位
已用 IC / 零件: NCN6001
主要屬性: 與 ISO 7816-3,EMV,GIE-CB 兼容
次要屬性: 符合 GSM 規(guī)定
已供物品:
其它名稱: NCN6001DTBEVBOS
NCN6001
http://onsemi.com
13
Read Register " READ_REG
The READ_REG register contains the data read from the
interface and from the external card. The selected register is
transferred to the MISO pin during the MOSI sequence
(CS = Low). Table 3 gives the bits definition.
Depending upon the programmed SPI_MODE, the
content of READ_REG is transferred on the MISO line
either on the Positive going (SPI_MODE = Special) or upon
the Negative going slope (SPI_MODE = Normal) of the
CLK_SPI signal. The external microcontroller shall discard
the three high bytes since they carry no valid data.
Table 3. MOSI AND MISO BITS IDENTIFICATIONS AND FUNCTIONS
MOSI
b7
b6
b5
b4
b3
b2
b1
b0
Operating Mode
0
1
0
1
0
1
0
1
0
1
0
RST
CLK
I/O
VCC
C4
VCC
C8
Asynchronous, Program Chip
Synchronous, Sets Card Bits
MISO
z
Card Detect
I/O
C4
C8
PWR Monitor
Read Back Data
ASYNCHRONOUS MODE
In this mode, the CRD_C4 and CRD_C8 pins are used to
define the physical addresses of the interfaces when a bank
of up to four NCN6001 share the same digital bus.
SYNCHRONOUS MODE
In this mode, CRD_C4 and CRD_C8 are connected to the
smart card and it is no longer possible to share the CS signal
with other device. Consequently, a dedicated Chip Select
signal must be provided when the interfaces operate in a
multiple operation mode (Figure 34).
On the other hand, since bits [b4 – b0] of the MOSI
register contain the smart card data, programming the
CRD_VCC output voltage shall be done by sending a
previous MOSI message according to Table 1 and Table 2.
The CRD_RST pin reflects the content of the MOSI
WRT_REG[b4] during the chip programming sequence.
Since this bit shall be Low to address the internal register of
the chip, care must be observed as this signal will be
immediately transferred to the CRD_RST pin.
Since no physical address can exist when the chip operates
in this mode, the MOSI register must use the format
%100XXXXX to program the chip (%100 prefix, XXXXX
data).
Example:
LDAA #%10010111
;set RST = H, CLK = 1/1, VCC = 5.0 V
STAA MOSI
LDAA #%11010011
;SYNC. Card: set RST = H, CLK = L, IO = L, C4 = H, C8= H
STAA MOSI
LDAA #%00111110
;ASYNC. Card: set RST = H, CLK =
, VCC = 3.0 V
STAA MOSI
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