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參數資料
| 型號： | NCP1603D100R2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 21/30頁 |
| 文件大小： | 302K |
| 描述： | IC CTLR PFC/PWM COMBO 16-SOIC |
| 產品變化通告： | Product Discontinuation 21/Jun/2007 |
| 標準包裝： | 2,500 |
| 模式： | 臨界傳導（CRM），間歇導電（DCM） |
| 頻率 - 開關： | 58kHz |
| 電流 - 啟動： | 17µA |
| 電源電壓： | 9 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
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NCP1603
http://onsemi.com
21
Figure 54 illustrates the standby detection circuitry and
its timing diagram. When standby condition happens (i.e.,
V
FB2
< 0.75 V), the controller will wait for a typical 125 ms
to ensure that the output power remains low for a while.
Then, the V
aux
is disabled to shut down the PFC section for
power saving. The V
aux
(or the PFC) restores when V
FB2
goes above 1.25 V immediately because V
FB2
can be
possibly above the 0.75 V threshold during standby
operation (referring to Figure 55) and the PFC section is
needed after the circuit restores from standby condition.
Figure 55. Timing Diagram in Standby Condition
V
CC2
V
FB2
I
D
Out2 goes low (no drain current) when V
FB2
< 0.75 V
V
CC2
needs to be above 7.7 V to ensure
proper operation of the controller and
main output within regulation
1.25 V
0.75 V
7.7 V
time
Figure 56. Block Diagram in Standby Operation in
PWM Section
CS2
FB2
Vcc2
Out2
PWM
R
S
+
2
3
13
clock
0.75 V
+
OR
Standby
Q
V
FB2
Figure 55 and 56 show the timing diagram and block
diagram of the standby operation respectively. A skipping
cycle behavior of the drain current is made by reset the
latch whenever V
FB2
is smaller than 0.75 V. When V
FB2
is
greater than 0.75 V, the duty ratio is modulated by the
PWM block that is illustrated in Figure 50.
PFC in Discontinuous/Critical Mode
The PFC section of the NCP1603 is NCP1601 that is
designed for lowpower PFC boost circuit in DCM or CRM
and takes advantages on both operating modes. DCM limits
the maximum switching frequency. It simplifies the
frontended EMI filter design. CRM limits the maximum
currents of diode, MOSFET and inductor. It reduces the
costs and improves the reliability of the circuit. This device
substantially exhibits unity power factor while operating in
DCM and CRM. It minimizes the number of external
components.
The PFC section primarily designed to operate in
fixedfrequency DCM. In the most stressful conditions,
CRM can be an alternative option that is without power
factor degradation. On the other hand, the PFC section can
be viewed as a CRM controller with a frequency clamp
(maximum switching frequency limit) alternative option
that is also without power factor degradation. In summary,
the PFC section can cover both CRM and DCM without
power factor degradation. Based on the selections of the
boost inductor and the oscillator frequency, the circuit is
capable of the following three applications.
1. CRM only by setting the oscillator frequency
higher than the CRM frequency range.
2. CRM and DCM by setting the oscillator
frequency somewhere within the CRM frequency
range.
3. DCM only by setting the oscillator frequency
lower than the CRM frequency range.
Figure 57. Timing Diagram of the PFC Stage
critical mode
DCM
DCM
time
current
time
time
time
V
in
V
ton
V
control
Inductor current, I
L
Input current, I
in
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