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參數(shù)資料
| 型號(hào)： | PCT1789N |
| 英文描述： | PCT303DL |
| 中文描述： | PCT303DL |
| 文件頁(yè)數(shù)： | 10/40頁(yè) |
| 文件大小： | 632K |
| 代理商： | PCT1789N |
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PC-TEL, Inc.
19
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL F
UNCTIONAL
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
the SB bit of register 1. In the 16-bit TX mode, the
hardware FC pin must be used to request secondary
transfers.
Figure 10 and Figure 11 illustrate the secondary frame
read cycle and write cycle, respectively. During a read
cycle, the R/W bit is high and the 5-bit address field
contains the address of the register to be read. The
contents of the 8-bit control register are placed on the
SDO signal. During a write cycle, the R/W bit is low and
the 5-bit address field contains the address of the
register to be written. The 8-bit data to be written
immediately follows the address on SDI. Only one
register can be read or written during each secondary
frame. See “303DL Control Registers” on page 43 for
the register addresses and functions.
In serial mode 2, the PCT303D operates as a slave
device, where the MCLK is an input, the SCLK is a no
connect, and the FSYNC is an input. In addition, the
RGDT/FSD pin operates as a delayed frame sync (FSD)
and the FC/RGDT pin operates as ring detect (RGDT).
Note that in this mode, FC operation is not supported.
For further details on operating the PCT303D as a slave
device, refer to “Multiple Device Support” on page 23.
Clock Generation Subsystem
The 303DL contains an on-chip clock generator. Using
a single MCLK input frequency, the 303DL can generate
all the desired standard modem sample rates, as well as
the common 11.025 kHz rate for audio playback.
The clock generator consists of two phase-locked loops
(PLL1 and PLL2) that achieve the desired sample
frequencies. Figure 12 on page 20 illustrates the clock
generator. The architecture of the dual PLL scheme
Figure 10 Secondary Communication Data Format - Read Cycle
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A
A
A
A
A
D
D
D
D
D
D
D
D
FSYNC
(mode 0)
SDI
SDO
1
0
0
R/W
FSYNC
(mode 1)
D7
D0
D15 D14 D13 D12 D11 D10 D9
D8
A
A
A
A
A
FSYNC
(mode 0)
SDI
SDO
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
D
D
D
D
D
D
D
D
R/W
FSYNC
(mode 1)
Figure 11 Secondary Communication Data Format - Write Cycle
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