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參數(shù)資料
| 型號： | PCT1789N |
| 英文描述： | PCT303DL |
| 中文描述： | PCT303DL |
| 文件頁數(shù)： | 24/40頁 |
| 文件大小： | 632K |
| 代理商： | PCT1789N |
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PC-TEL, Inc.
46
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL C
ONTROL
R
EGISTERS
!
PRELIMINARY
PRELIMINARY
PLL1 Multiply M1
(Register 8, R/W)
Reset settings: 00h (serial mode 0,1)
Reset settings: 13h (serial mode 2)
Bit Definitions:
PLL2 Divide/Multiply N2/M2
(Register 9, R/W)
Reset settings: 00h (serial mode 0, 1, 2)
Bit Definitions:
PLL Control
(Register 10, R/W)
Reset settings: 00h
Bit Definitions:
Chip Revision
(Register 11, R)
Reset settings: N/A
Bit Definitions:
Multiplier M1
7
6
5
4
3
2
1
0
Bits
Name
Multiplier M1
Description
Contains the (value – 1) for determining the output frequency on PLL1.
7:0
Divider N2
Multiplier M2
7
6
5
4
3
2
1
0
Bits
Name
Divider N2
Multiplier M2
Description
Contains the (value – 1) for determining the output frequency on PLL2.
Contains the (value – 1) for determining the output frequency on PLL2.
7:4
3:0
Reserved
4
CGM
0
7
6
5
3
2
1
Bits
Name
Reserved
CGM
Description
Reserved. Read returns zero.
Clock Generation Mode.
1 = A 25/16 ratio is applied to the PLL allowing for a more flexible choice of
MCLK frequencies while slowing down the PLL lock time.
0 = No additional ratio is applied to the PLL and faster lock times are possible.
7:1
0
Reserved
REVA
7
6
5
4
3
2
1
0
Bits
Name
Reserved
REVA
Description
Reserved. Read returns zero.
Chip revision. Read-only.
Four-bit value indicating the revision of the PCT303D (DSP-side) silicon.
1000 = Revision A
1001 = Revision B
7:4
3:0
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