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參數資料
| 型號： | PCT1789N |
| 英文描述： | PCT303DL |
| 中文描述： | PCT303DL |
| 文件頁數： | 12/40頁 |
| 文件大小： | 632K |
| 代理商： | PCT1789N |
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PC-TEL, Inc.
21
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL F
UNCTIONAL
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
After the first PLL has been setup, the second PLL can
be programmed easily. The values for N2 and M2
(register 9) are shown in Table 9. N2 and M2 are 4-bit
unsigned values.
When programming the registers of the clock generator,
the order of register writes is important. For PLL1
updates, N1 (register 7) must always be written first,
immediately followed by a write to M1 (register 8). For
PLL2, the CGM bit must set as desired prior to writing
N2/M2 (register 9). Changes to CGM only take effect
when N2/M2 are written.
NOTE: The values shown in Table 9 and Table 10
satisfy
the
equations
programming the registers for N1, M1, N2, and M2, the
value placed in these registers must be one less than
the value calculated from the equations. For example,
for CGM = 0 with a MCLK of 48.0 MHz, the values
placed in the N1 and M1 registers would be 7Ch and
5Fh, respectively. If CGM = 1, a non-zero value must be
programmed to register 9 in order for the 16/25 ratio to
take effect.
above.
However,
when
PLL Lock Times
The 303DL changes sample rates very quickly.
However, lock time varies based on the programming of
the clock generator. The major factor contributing to PLL
lock time is the CGM bit. When the CGM bit is used (set
to one), PLL2 locks slower than when CGM is zero. The
following relationships describe the boundaries on PLL
locking time:
PLL1 lock time < 1 ms (CGM = 0,1)
PLL2 lock time <100 μs (CGM = 0)
PLL2 lock time <1 ms (CGM = 1)
For modem designs, it is recommended that PLL1 be
programmed
during
initialization.
programming of PLL1 is necessary. The CGM bit and
PLL2 can be programmed for the desired initial sample
rate, typically 7200 Hz. All further sample rate changes
are then made by simply writing to register 9 to update
PLL2.
No
further
The final design consideration for the clock generator is
the update rate of PLL1. The following criteria must be
satisfied in order for the PLLs to remain stable:
Where F
UP1
is shown in Figure 12 on page 20.
Setting Generic Sample Rates
The above clock generation description focuses on the
common modem sample rates. An application may
require a sample rate not listed in Table 9, such as the
common audio rate of 11.025 kHz. The restrictions and
equations above still apply; however, a more generic
relationship between MCLK and Fs (the desired sample
rate) is needed. The following equation describes this
relationship:
where
Fs
is the sample frequency,
ratio
is 1 for CGM=0
and 25/16 for CGM = 1, and all other symbols are shown
in Figure 12 on page 20.
FUP
1
FMCLK
N
1
(
)
=
144
kHz
≥
Table 10 MCLK Examples
MCLK
(MHz)
1.8432
4.0000
4.0960
5.0688
6.0000
6.1440
8.1920
9.2160
10.0000
10.3680
11.0592
12.2880
14.7456
16.0000
18.4320
24.5760
25.8048
33.8688
44.2368
46.0800
47.9232
48.0000
56.0000
60.0000
N1
M1
CGM
1
5
1
11
5
1
32
1
25
9
3
1
2
5
1
32
7
147
96
5
13
125
35
25
20
72
9
80
48
6
225
4
144
32
10
3
5
18
2
75
10
160
125
4
10
96
36
24
0
1
0
0
1
0
1
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
1
N1 N2
M1 M2
ratio
Fs
MCLK
5 1024
=
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