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參數資料
| 型號： | PCT1789N |
| 英文描述： | PCT303DL |
| 中文描述： | PCT303DL |
| 文件頁數： | 11/40頁 |
| 文件大?。?/td> | 632K |
| 代理商： | PCT1789N |
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PC-TEL, Inc.
20
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
303DL F
UNCTIONAL
D
ESCRIPTION
!
PRELIMINARY
PRELIMINARY
allows for fast lock time on initial start-up, fast lock time
when changing modem sample rates, high noise
immunity, and the ability to change modem sample rates
with a single register write. A large number of MCLK
frequencies between 1 MHz and 60 MHz are supported.
In serial mode 2, the PCT303D operates as a slave
device. The clock generator is configured (by default) to
set the SCLK output equal to the MCLK input. The net
effect is the clock generator multiplies the MCLK input
by 20. For further details of slave mode operation, refer
to “Multiple Device Support” on page 23.
Programming the Clock Generator
As noted in Figure 12, the clock generator must output a
clock equal to 1024*Fs, where Fs is the desired sample
rate. The 1024*Fs clock is determined through
programming of the following registers:
Register 7—N1 divider, 8 bits.
Register 8—M1 divider, 8 bits.
Register 9—N2/M2 dividers, 4 bits/4 bits.
Register 10—CGM, 1 bit.
When using the 303DL for modem applications, the
clock generator can be programmed to allow for a single
register write to change the modem sampling rate.
These standard sample rates are shown in Table 9. The
programming method is described below.
The main design consideration is the generation of a
base frequency, defined as the following:
N1 (register 7) and M1 (register 8) are 8-bit unsigned
values. F
MCLK
is the clock provided to the MCLK pin.
Table 10 lists several standard crystal oscillator rates
that could be supplied to MCLK. This list simply
represents a sample of MCLK frequency choices. Many
more are possible.
÷
M1
VCO1
P
D
÷
25
÷
N2
P
D
0
1
0
1
÷
16
MCLK
8 bits
8 bits
F
UP1
F
PLL1
F
PLL2
4 bits
1024Fs
PLL1
F
UP2
CGM
CGM
÷
N1
÷
5
÷
M2
4 bits
PLL2
VCO2
Figure 12 Clock Generation Subsystem
Table 9 N2, M2 Values (CGM = 0, 1)
Fs (Hz)
7200
8000
8229
8400
9000
9600
10286
N2
2
9
7
6
4
3
7
M2
2
10
8
7
5
4
10
FBase
FMCLK
M
1
N
1
36.864
MHz CGM
,
0
=
=
=
FBase
FMCLK
M
1
16
N
1 25
36.864
MHz CGM
,
1
=
=
=
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