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| 型號(hào)： | Q67127-C2036SAB-C161R1-L16M |
| 英文描述： | IC-SM-16 BIT CPU |
| 中文描述： | 集成電路的Sm - 16位CPU |
| 文件頁(yè)數(shù)： | 15/121頁(yè) |
| 文件大小： | 1000K |
| 代理商： | Q67127-C2036SAB-C161R1-L16M |
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Introduction
C501
Semiconductor Group
1-9
PSEN
32
29
26
O
The Program Store Enable
output is a control signal that enables the
external program memory to the bus
during external fetch operations. It is
activated every six oscillator periods
except during external data memory
accesses. Remains high during internal
program execution.
RESET
10
9
4
I
RESET
A high level on this pin for two machine
cycles while the oscillator is running
resets the device. An internal diffused
resistor to
V
SS
permits power-on reset
using only an external capacitor to
V
CC
.
The
Address Latch Enable
output is used for latching the low-byte of
the address into external memory during
normal operation. It is activated every six
oscillator periods except during an
external data memory access.
For the C501-1E this pin is also the
program pulse input (PROG) during OTP
memory programming.
ALE/PROG 33
30
27
I/O
EA/
V
PP
35
31
29
I
External Access Enable
When held at high level, instructions are
fetched from the internal ROM (C501-1R
and C501-1E) when the PC is less than
2000H. When held at low level, the C501
fetches all instructions from external
program memory. For the C501-L this
pin must be tied low.
This pin also receives the programming
supply voltage
V
PP
during OTP memory
programming (C501-1E) only).
*) I
= Input
O = Output
Table 1-1
Pin Definitions and Functions
(cont’d)
Symbol
Pin Number
I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
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