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參數資料
| 型號： | Q67127-C2036SAB-C161R1-L16M |
| 英文描述： | IC-SM-16 BIT CPU |
| 中文描述： | 集成電路的Sm - 16位CPU |
| 文件頁數： | 31/121頁 |
| 文件大小： | 1000K |
| 代理商： | Q67127-C2036SAB-C161R1-L16M |
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External Bus Interface
C501
Semiconductor Group
4-4
4.2
PSEN, Program Store Enable
The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the
CPU is accessing external program memory, PSEN is activated twice every cycle (except during a
MOVX instruction) no matter whether or not the byte fetched is actually needed for the current
instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle,
including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN
cycle, including activation and deactivation of ALE and PSEN takes 3 oscillator periods. The
execution sequence for these two types of read cycles is shown in
figure 4-1 a)
and
b)
.
4.3
ALE, Address Latch Enable
The main function of ALE is to provide a properly timed signal to latch the low byte of an address
from P0 into an external latch during fetches from external memory. The address byte is valid at the
negative transition of ALE. For that purpose, ALE is activated twice every machine cycle. This
activation takes place even if the cycle involves no external fetch. The only time no ALE pulse
comes out is during an access to external data memory when RD/WR signals are active. The first
ALE of the second cycle of a MOVX instruction is missing (see
figure 4-1 b
). Consequently, in any
system that does not use data memory, ALE is activated at a constant rate of 1/6 of the oscillator
frequency and can be used for external clocking or timing purposes.
4.4
Overlapping External Data and Program Memory Spaces
In some applications it is desirable to execute a program from the same physical memory that is
used for storing data. In the C501 the external program and data memory spaces can be combined
by AND-ing PSEN and RD. A positive logic AND of these two signals produces an active low read
strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the
RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle.
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