- 您現在的位置：買賣IC網 > PDF目錄361239 > Q67127-C2036SAB-C161R1-L16M IC-SM-16 BIT CPU PDF資料下載
參數資料
| 型號： | Q67127-C2036SAB-C161R1-L16M |
| 英文描述： | IC-SM-16 BIT CPU |
| 中文描述： | 集成電路的Sm - 16位CPU |
| 文件頁數： | 44/121頁 |
| 文件大小： | 1000K |
| 代理商： | Q67127-C2036SAB-C161R1-L16M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁
Semiconductor Group
6-10
On-Chip Peripheral Components
C501
6.1.3 Port Handling
6.1.3.1 Port Timing
When executing an instruction that changes the value of a port latch, the new value arrives at the
latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by
their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the
value it noticed during the previous phase 1). Consequently, the new value in the port latch will not
appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle.
When an instruction reads a value from a port pin (e.g. MOV A, P1) the port pin is actually sampled
in state 5 phase 1 or phase 2 depending on port and alternate functions.
Figure 6-10
illustrates this
port timing. lt must be noted that this mechanism of sampling once per machine cycle is also used
if a port pin is to detect an “edge”, e.g. when used as counter input. In this case an “edge” is detected
when the sampled value differs from the value that was sampled the cycle before. Therefore, there
must be met certain requirements on the pulse length of signals in order to avoid signal “edges” not
being detected. The minimum time period of high and low level is one machine cycle, which
guarantees that this logic level is noticed by the port at least once.
Figure 6-10
Port Timing
MCT03231
P1
P2
S4
S5
P2
P1
S6
P2
P1
S1
P2
P1
S2
P2
P1
S3
P2
P1
XTAL2
Input sampled:
e.g. MOV A, P1
Old Data
New Data
Port
P1 active for 1 State
(driver transistor)
相關PDF資料 |
PDF描述 |
|---|---|
| Q67120-C2200 | 16-Bit Single-Chip Microcontroller Bare Die Delivery |
| Q67120-C1054 | High Speed CMOS Logic Triple 3-Input NOR Gates 14-SOIC -55 to 125 |
| Q67120-C1056 | High Speed CMOS Logic Triple 3-Input NOR Gates 14-SOIC -55 to 125 |
| Q67120-C2002 | High Speed CMOS Logic Octal D-Type Flip-Flops with Reset 20-SOIC -55 to 125 |
| Q67120-C2003 | 8-Bit CMOS Microcontroller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| Q67127-C2056 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| Q67127-C2057 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| Q67127-C2058 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| Q67127-C2060 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| Q67127-C2061 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
發布緊急采購，3分鐘左右您將得到回復。