- 您現在的位置：買賣IC網 > PDF目錄361239 > Q67127-C2036SAB-C161R1-L16M IC-SM-16 BIT CPU PDF資料下載
參數資料
| 型號： | Q67127-C2036SAB-C161R1-L16M |
| 英文描述： | IC-SM-16 BIT CPU |
| 中文描述： | 集成電路的Sm - 16位CPU |
| 文件頁數： | 20/121頁 |
| 文件大小： | 1000K |
| 代理商： | Q67127-C2036SAB-C161R1-L16M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁
Semiconductor Group
2-4
Fundamental Structure
C501
2.2
CPU Timing
A machine cycle of the C501 consists of 6 states (12 oscillator periods). Each state is devided into
a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase
2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbererd S1P1 (state 1,
phase 1) through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically,
arithmetic and logically operations take place during phase 1 and internal register-to-register
transfers take place during phase 2.
The diagrams in
figure 2-7
show the fetch/execute timing related to the internal states and phases.
Since these internal clock signals are not user-accessible, the XTAL2 oscillator signals and the ALE
(address latch enable) signal are shown for external reference. ALE is normally activated twice
during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1.
Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction
register. If it is a two-byte instruction, the second reading takes place during S4 of the same
machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would
be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In
any case, execution is completed at the end of S6P2.
Figures 2-7 (a)
and
(b)
show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle
instruction.
Most C501 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only
instructions that take more than two cycles to complete; they take four cycles. Normally two code
bytes are fetched from the program memory during every machine cycle. The only exception to this
is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses
external data memory. During a MOVX, the two fetches in the second cycle are skipped while the
external data memory is being addressed and strobed.
Figure 2-7 c)
and
d)
show the timing for a
normal 1-byte, 2-cycle instruction and for a MOVX instruction.
相關PDF資料 |
PDF描述 |
|---|---|
| Q67120-C2200 | 16-Bit Single-Chip Microcontroller Bare Die Delivery |
| Q67120-C1054 | High Speed CMOS Logic Triple 3-Input NOR Gates 14-SOIC -55 to 125 |
| Q67120-C1056 | High Speed CMOS Logic Triple 3-Input NOR Gates 14-SOIC -55 to 125 |
| Q67120-C2002 | High Speed CMOS Logic Octal D-Type Flip-Flops with Reset 20-SOIC -55 to 125 |
| Q67120-C2003 | 8-Bit CMOS Microcontroller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| Q67127-C2056 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| Q67127-C2057 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| Q67127-C2058 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| Q67127-C2060 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
| Q67127-C2061 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller |
發布緊急采購，3分鐘左右您將得到回復。