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參數資料
型號: SC424MLTRT
廠商: Semtech
文件頁數: 12/29頁
文件大小: 496K
描述: IC REG DL BUCK/LINEAR 28MLPQ
標準包裝: 1
系列: SmartDrive™
拓撲: 降壓(降壓)(1),線性(LDO)(1)
功能: 任何功能
輸出數: 2
頻率 - 開關: 200kHz ~ 1MHz
電壓/電流 - 輸出 1: 可調至 0.75V,6A
電壓/電流 - 輸出 2: 5V,150mA
帶 LED 驅動器:
帶監控器:
帶序列發生器:
電源電壓: 3 V ~ 28 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-VFQFN 裸露焊盤
供應商設備封裝: 28-MLPQ(4x4)
包裝: 標準包裝
其它名稱: SC424MLDKR
SC414/SC424
12
Pin Descriptions
Pin #    Pin Name  Pin Function
1
FB
Feedback input for switching regulator used to program the output voltage  connect to an external resis-
tor divider from VOUT to AGND.
2
V5V
Bias input for internal analog circuits and gate drives  connect to external 3V or 5V supply or bias connec-
tion to VLDO.
3, 26, PAD 1    AGND    Analog ground
4
VOUT    Switcher output voltage sense pin, and also the input to the internal switch-over between VOUT and VLDO.
5, 8-11
PAD 2
VIN    Input supply voltage
6
VLDO    5V LDO output
7
BST
Bootstrap pin  connect a capacitor from BST to LXBST to develop the fl oating supply for the high-side gate
drive.
12
LXBST    LX Boost  connect to the BST capacitor.
15,20, 21,
PAD 3
LX    Switching (phase) node
13, 14, 16-19    PGND    Power ground
22
PGOOD
Open-drain power good indicator  high impedance indicates power is good. An external pull-up
resistor is required.
23
ILIM    Current limit sense pin  used to program the current limit by connecting a resistor from ILIM to LXS.
24
LXS    LX sense  connects to RILIM resistor
25
EN/PSV
Enable/power save input for the switching regulator  connect to AGND to disable the switching regula-
tor. Float to operate in forced continuous mode (power save disabled). For SC414, connect to V5V to operate
with ultrasonic power save mode enabled. For SC424, connect to V5V to operate with power save mode
enabled with no minimum frequency.
27
TON    On-time programming input  set the on-time by connecting through a resistor to AGND
28
ENL
Enable input for the LDO  connect ENL to AGND to disable the LDO. Drive with logic to +3V for logic con-
trol, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.
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