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參數資料
| 型號： | SC424MLTRT |
| 廠商： | Semtech |
| 文件頁數： | 20/29頁 |
| 文件大小： | 496K |
| 描述： | IC REG DL BUCK/LINEAR 28MLPQ |
| 標準包裝： | 1 |
| 系列： | SmartDrive™ |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數： | 2 |
| 頻率 - 開關： | 200kHz ~ 1MHz |
| 電壓/電流 - 輸出 1： | 可調至 0.75V，6A |
| 電壓/電流 - 輸出 2： | 5V，150mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 無 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-MLPQ（4x4） |
| 包裝： | 標準包裝 |
| 其它名稱： | SC424MLDKR |
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SC414/SC424
20
LDO Switch-Over Operation
The SC414/SC424 includes a switch-over function for the
LDO. The switch-over function is designed to increase
effi ciency by using the more effi cient DC-DC converter to
power the LDO output, avoiding the less efficient LDO
regulator when possible. The switch-over function con-
nects the VLDO pin directly to the VOUT pin using an
internal switch. When the switch-over is complete the
LDO is turned off , which results in a power savings and
maximizes effi ciency. If the LDO output is used to bias the
SC414/SC424, then after switch-over the device is self-
powered from the switching regulator with the LDO
turned off .
The switch-over logic waits for 32 switching cycles before
it starts the switch-over. There are two methods that
determine the switch-over of V
LDO
to V
OUT
.
In the fi rst method, the LDO is already in regulation and
the DC-DC converter is later enabled. As soon as the
PGOOD output goes high, the 32 cycle counter is started.
The voltages at the VLDO and VOUT pins are then com-
pared; if the two voltages are within ?00mV (typically) of
each other, within 32 cylces, the VLDO pin connects to the
VOUT pin using an internal switch, and the LDO is turned
off .
In the second method, the DC-DC converter is already
running and the LDO is enabled. In this case the 32 cycles
are started as soon as the LDO reaches 90% of its fi nal
value. At this time, the VLDO and VOUT pins are compared,
and if within ?00mV (typically) the switch-over occurs
and the LDO is turned off .
Switch-over Limitations on VOUT and VLDO
Because the internal switch-over circuit always compares
the VOUT and VLDO pins at start-up, there are voltage
limitations on permissible combinations of these pins.
Consider the situation where V
OUT
is programmed to 4.7V.
After start-up, the device would connect VOUT to VLDO
and disable the LDO, since the two voltage are within the
?00mV switch-over window. To avoid unwanted switch-
over, the minimum diff erence between the voltages for
V
OUT
and V
LDO
should be ?00mV.
Switch-over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that
are inherent to its construction, as shown in Figure 11.
Switchover
MOSFET
Parasitic diode
Parasitic diode
V5V
V
LDO
V
OUT
Switchover
control
Figure 11 Switch-over MOSFET Parasitic Diodes
There are some important design rules that must be fol-
lowed to prevent forward bias of these diodes. The fol-
lowing two conditions need to be satisfi ed in order for the
parasitic diodes to stay off .
V5V e V
LDO
V5V e V
OUT
If either V
LDO
or V
OUT
is higher than V5V, then the respective
diode will turn on and the SC414/SC424 operating current
will flow through this diode. This has the potential of
damaging the device.
ENL pin and V
IN
UVLO
The ENL pin also acts as the switcher under-voltage
lockout for the V
IN
supply. The V
IN
UVLO voltage is pro-
grammable via a resistor divider at the VIN, ENL, and AGND
pins.
ENL is the enable/disable signal for the LDO. In order to
implement the V
IN
UVLO there is also a timing requirement
that needs to be satisfi ed.
If the ENL pin transitions low within 2 switching cycles and
is < 1V, then the LDO will turn off but the switcher remains
on. If ENL goes below the V
IN
UVLO threshold and stays
above 1V, then the switcher will turn off but the LDO
remains on.
The V
IN
UVLO function has a typical threshold of 2.6V on
the V
IN
rising edge. The falling edge threshold is 2.4V.
"
"
Applications Information (continued)
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