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參數(shù)資料
| 型號： | SC424MLTRT |
| 廠商： | Semtech |
| 文件頁數(shù)： | 25/29頁 |
| 文件大小： | 496K |
| 描述： | IC REG DL BUCK/LINEAR 28MLPQ |
| 標準包裝： | 1 |
| 系列： | SmartDrive™ |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 200kHz ~ 1MHz |
| 電壓/電流 - 輸出 1： | 可調(diào)至 0.75V，6A |
| 電壓/電流 - 輸出 2： | 5V，150mA |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-MLPQ（4x4） |
| 包裝： | 標準包裝 |
| 其它名稱： | SC424MLDKR |
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SC414/SC424
25
Applications Information (continued)
Using Ceramic Output Capacitors
When applications use ceramic output capacitors, the ESR
is normally too small to meet the previously stated ESR
criteria. In these applications it is necessary to add a small
virtual ESR network composed of two capacitors and one
resistor, as shown in Figure 14. This network creates a
ramp voltage across C
L
, analogous to the ramp voltage
generated across the ESR of a standard capacitor. This
ramp is then capacitively coupled into the FB pin via
capacitor C
C
.
R1
R2
FB
pin
C
C
C
OUT
L
Low-
side
High-
side
C
L
R
L
Figure 14 Virtual ESR Ramp Current
Output Voltage Dropout
The output voltage adjustable range for continuous-con-
duction operation is limited by the fi xed 320ns (typical)
minimum off -time. When working with low input volt-
ages, the duty-factor limit must be calculated using worst-
case values for on and off times.
The duty-factor limitation is shown by the next equation.
)
MIN
(
OFF
)
MIN
(
ON
)
MIN
(
ON
T
T
T
DUTY
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy V
OUT
Controller
Three factors aff ect V
OUT
accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator off set is trimmed so that under static condi-
tions it trips when the feedback pin is 750mV, 1%.
The on-time pulse from the SC414/SC424 in the design
example is calculated to give a pseudo-fi xed frequency of
250kHz. Some frequency variation with line and load is
expected. This variation changes the output ripple
voltage. Because constant on-time converters regulate to
the valley of the output ripple, ?of the output ripple
appears as a DC regulation error. For example, if the
output ripple is 50mV with V
IN
= 6 volts, then the measured
DC output will be 25mV above the comparator trip point.
If the ripple increases to 80mV with V
IN
= 25V, then the
measured DC output will be 40mV above the comparator
trip. The best way to minimize this eff ect is to minimize
the output ripple.
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capaci-
tor. This trace resistance should be optimized so that at
full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capaci-
tance because the voltage excursions due to load steps
are reduced as seen at the load.
The use of 1% feedback resistors may result in up to an
additional 1% error. If tighter DC accuracy is required,
resistors with lower tolerances should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor eff ect on the DC output voltage. The output ESR
also aff ects the output ripple and thus has a minor eff ect
on the DC output voltage.
Switching Frequency Variations
The switching frequency will vary depending on line and
load conditions. The line variations are a result of fi xed
propagation delays in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
V
IN
increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net eff ect is
that frequency tends to falls slightly with increasing input
voltage.
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