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參數資料
| 型號： | SC424MLTRT |
| 廠商： | Semtech |
| 文件頁數： | 19/29頁 |
| 文件大小： | 496K |
| 描述： | IC REG DL BUCK/LINEAR 28MLPQ |
| 標準包裝： | 1 |
| 系列： | SmartDrive™ |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數： | 2 |
| 頻率 - 開關： | 200kHz ~ 1MHz |
| 電壓/電流 - 輸出 1： | 可調至 0.75V，6A |
| 電壓/電流 - 輸出 2： | 5V，150mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 無 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-MLPQ（4x4） |
| 包裝： | 標準包裝 |
| 其它名稱： | SC424MLDKR |
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SC414/SC424
19
During soft-start the regulator turns off the low-side
MOSFET on any cycle if the inductor current falls to zero.
This prevents negative inductor current, allowing the
device to start into a pre-biased output. This soft start
operation is implemented even if FCM is selected. FCM
operation is allowed only after PGOOD is high.
Power Good Output
The power good (PGOOD) output is an open-drain output
which requires a pull-up resistor. When the output voltage
is 10% below the nominal voltage, PGOOD is pulled low. It
is held low until the output voltage returns to the nominal
voltage. PGOOD is held low during start-up and will not
be allowed to transition high until soft-start is completed
(when V
FB
reaches 750mV) and typically 4ms has passed.
PGOOD will transition low if the V
FB
pin exceeds +20% of
nominal, which is also the over-voltage shutdown thresh-
old (900mV). PGOOD also pulls low if the EN/PSV pin is
low when V5V is present.
Output Over-Voltage Protection
Over-Voltage Protection (OVP) becomes active as soon as
the device is enabled. The threshold is set at 750mV + 20%
(900mV). When V
FB
exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off , until the EN/PSV input
is toggled or V5V is cycled. There is a 5約 delay built into
the OVP detector to prevent false transitions. PGOOD is
also low after an OVP event.
Output Under-Voltage Protection
When V
FB
falls to 75% of its nominal voltage (falls to
562.5mV) for eight consecutive clock cycles, the switcher
is shut off and the DH and DL drives are pulled low to turn
off the MOSFETs. The controller stays off until EN/PSV is
toggled or V5V is cycled.
V5V UVLO, and POR
Under-Voltage Lock-Out (UVLO) circuitry inhibits switch-
ing and tri-states the DH/DL drivers until V5V rises above
2.9V. An internal Power-On Reset (POR) occurs when V5V
exceeds 2.9V, which resets the fault latch and soft-start
counter to begin the soft-start cycle. The SC414/SC424
then begins a soft-start cycle. The PWM will shut off if V5V
falls below 2.7V.
LDO Regulator
The device features an integrated LDO regulator with a
fixed output voltage of 5V. There is also an enable pin
(ENL) for the LDO that provides independent control. The
LDO voltage can also be used to provide the bias voltage
for the switching regulator.
A minimum capacitance of 1糉 referenced to AGND is
normally required at the output of the LDO for stability. If
the LDO is providing bias power to the device, then a
minimum 0.1糉 capacitor referenced to AGND is required,
along with a minimum 1糉 capacitor referenced to PGND
to fi lter the gate drive pulses. Refer to the layout guide-
lines section.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
ENL pin
VLDO output
V
IN
input voltage
When the ENL pin is high, the LDO will begin start-up, see
Figure 10. During the initial phase, when the LDO output
voltage is near zero, the LDO initiates a current-limited
start-up (typically 85mA) to charge the output capacitor.
When V
LDO
has reached 90% of the fi nal value, the LDO
current limit is increased to ~200mA and the LDO output
is quickly driven to the nominal value by the internal LDO
regulator.
V
VLDO
Final
90% of V
VLDO
Final
Constant current startup
Voltage regulating with
~200mA current limit
Figure 10 LDO Start-Up
1.
2.
3.
Applications Information (continued)
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