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參數資料
| 型號： | SC424MLTRT |
| 廠商： | Semtech |
| 文件頁數： | 26/29頁 |
| 文件大小： | 496K |
| 描述： | IC REG DL BUCK/LINEAR 28MLPQ |
| 標準包裝： | 1 |
| 系列： | SmartDrive™ |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數： | 2 |
| 頻率 - 開關： | 200kHz ~ 1MHz |
| 電壓/電流 - 輸出 1： | 可調至 0.75V，6A |
| 電壓/電流 - 輸出 2： | 5V，150mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 無 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-MLPQ（4x4） |
| 包裝： | 標準包裝 |
| 其它名稱： | SC424MLDKR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁第29頁
SC414/SC424
26
Applications Information (continued)
VOUT Plane
on Top layer
L
C
IN
CFF
RFB2
RFB1
RILIM
LX plane on inner
or bottom layer
All components
shown Top Side
AGND plane on
inner layer
V
IN
plane on inner
or bottom layer
RES_GND AGND connects
to PGND close to SC414/SC424
Pin 1 marking
SC414/SC424 with
vias for LX, AGND,
VIN
PGND on inner
or bottom layer
PGND
C
OUT
Note: This figure is not
to scale
Figure 15 PCB Layout
The switching frequency also varies with load current as a
result of the power losses in the MOSFETs and the induc-
tor. For a conventional PWM constant-frequency con-
verter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. A constant on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing
energy from V
IN
as losses increase). The on-time is essen-
tially constant for a given V
OUT
and V
IN
combination, to
off set the losses the off -time will tend to reduce slightly as
load increases. The net eff ect is that switching frequency
increases slightly with increasing load.
PCB Layout Guidelines
The optimum layout for the SC414/SC424 is shown in
Figure 15. This layout shows an integrated FET buck regu-
lator with a maximum current of 6A. The total PCB area is
approximately 20 x 25 mm.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
IC Decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
BST, ILIM, and LX
Capacitors and Current Loops
IC Decoupling Capacitors
A 0.1 糉 capacitor must be located as close as
possible to the IC and directly connected to pins
2 (V5V) and 3 (AGND).
"
"
"
"
"
"
"
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