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參數資料
| 型號： | TFP403PZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 14/20頁 |
| 文件大小： | 496K |
| 代理商： | TFP403PZPG4 |
TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A DECEMBER 2000 REVISED OCTOBER 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
_
+
Latch
Channel 2
_
+
Latch
Channel 1
_
+
Latch
Channel 0
_
+
PLL
Data Recovery
and
Synchronization
TMDS
Decoder
CH2(0-9)
CH1(0-9)
CH0(0-9)
Panel
Interface
RED(0-7)
CTL3
CTL2
GRN(0-7)
CTL1
BLUE(0-7)
VSYNC
HSYNC
QE(0-23)
QO(0-23)
ODCK
DE
SCDT
CTL2
CTL1
VSYNC
HSYNC
1.8 V
Regulator
3.3 V
Internal 50-
Termination
3.3 V
Rx2+
Rx2-
Rx1+
Rx1-
Rx0+
Rx0-
RxC+
RxC-
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
79
GND
Analog ground—Ground reference and current return for analog circuitry
AVDD
82,85,88,
91
VDD
Analog VDD—Power supply for analog circuitry. Nominally 3.3 V
CAP
67
VDD
Bypass capacitor—4.7
F tantalum and 0.01 F ceramic connected to ground. This capacitor is optional for
the TFP403, but is required for the TFP501.
CTL[2:1]
41,40
DO
General-purpose control signals—Used for user defined control. In normal mode CTL1 is not powered down
via PDO.
DE
46
DO
Output data enable—Used to indicate time of active video display versus nonactive display or blank time.
During blank, only HSYNC, VSYNC, and CTL1-2 are transmitted. During times of active display, or nonblank,
only pixel data, QE[23:0] and QO[23:0], is transmitted.
High : Active display time
Low: Blank time
DFO
1
DI
Output clock data format—Controls the output clock (ODCK) format for either TFT or DSTN panel support. For
TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high; otherwise
ODCK is held low when DE is low.
High : DSTN support/ODCK held low when DE = low
Low: TFT support/ODCK runs continuously.
DGND
5,39,68
GND
Digital ground—Ground reference and current return for digital core
DVDD
6,38
VDD
Digital VDD—Power supply for digital core. Nominally 3.3 V
HSYNC
48
DO
Horizontal sync output
OCK_INV
100
DI
ODCK polarity—Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals
(HSYNC, VSYNC, DE, CTL1-2 ) are latched
Normal mode:
High : Latches output data on rising ODCK edge
Low : Latches output data on falling ODCK edge
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